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Parallel forwarding for efficient bandwidth utilization in networks-on-chip
School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran.
Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran.
Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology (KTH), Stockholm, Sweden.
2017 (English)In: Lect. Notes Comput. Sci., Springer Verlag , 2017, 152-163 p.Conference paper (Refereed)
Abstract [en]

Networks-on-chip (NoC) provide a scalable and power-efficient communication infrastructure for different computing chips, ranging from fully customized multi/many-processor systems-on-chip (MPSoCs) to general-purpose chip multiprocessors (CMPs). A common aspect in almost all NoC workloads is the varying size of data transmitted by each transaction: while large data blocks are transferred as multiple-flit packets, a part of the traffic consists of short data segment (control data) that does not even fill a single flit. In conventional NoCs, switch allocator assigns/ grants a switch output (and the link connected to it) to a single flit at each cycle, even if the flit is shorter than the link bit-width. In this paper, we propose a novel NoC architecture that enables routers to simultaneously send two short flits on the same link, effectively utilizing the link bandwidth that otherwise would be wasted. To this end, new crossbar, virtual channel (VC), and switch allocator architectures are presented to support parallel short packet forwarding on NoC links. Simulation results using synthetic and realistic workloads show that the proposed architecture improves the NoC performance by up to 24%.

Place, publisher, year, edition, pages
Springer Verlag , 2017. 152-163 p.
Series
Lecture Notes in Computer Science, ISSN 0302-9743 ; 10172 LNCS
Keyword [en]
Bandwidth utilization, Heterogeneous packet size, Network-on-Chip, Bandwidth, Communication channels (information theory), Computer architecture, Network architecture, Routers, Servers, System-on-chip, Band-width utilization, Efficient bandwidth, General purpose chips, NoC architectures, Packet size, Parallel forwarding, Power-efficient communications, Proposed architectures
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:mdh:diva-35059DOI: 10.1007/978-3-319-54999-6_12ScopusID: 2-s2.0-85014843599ISBN: 9783319549989 OAI: oai:DiVA.org:mdh-35059DiVA: diva2:1083944
Conference
30th International Conference on Architecture of Computing Systems, ARCS 2017; Vienna; Austria; 3 April 2017 through 6 April 2017
Available from: 2017-03-23 Created: 2017-03-23 Last updated: 2017-03-27Bibliographically approved

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
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  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
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More languages
Output format
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