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Schedule Synthesis for Next Generation Time-Triggered Networks
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1228-5176
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. IS (Embedded Systems).ORCID iD: 0000-0002-4987-7669
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. IS (Embedded Systems).ORCID iD: 0000-0002-7235-6888
TTTech Computertechnik AG.
2017 (English)Report (Other academic)
Abstract [en]

For handling frame transmissions in highly deterministic real-time networks, i.e. networks requiring low communication latency and minimal jitter, an offline time-triggered schedule indicating the dispatch times of all frames can be used. Generation of such an offline schedule is known to be a NPcomplete problem, with complexity driven by the size of the network, the number and complexity of the traffic temporal constraints, and link diversity (for instance, coexistence of wired and wireless links). As embedded applications become more complex and extend over larger geographical areas, there is a need to deploy larger real-time networks, but existing schedule synthesis mechanisms do not scale satisfactorily to the sizes of these networks, constituting a potential bottleneck for system designers. In this paper, we present an offline synthesis tool that overcomes this limitation and is capable of generating time-triggered schedules for networks with hundreds of nodes and thousands of temporal constraints, also for systems where wired and wireless links are combined. This tool models the problem with linear arithmetic constraints and solves them using a Satisfiability Modulo Theory (SMT) solver, a powerful general purpose tool successfully used in the past for synthesizing time-triggered schedules. To cope with complexity, our algorithm implements a segmented approach that divides the total problem into easily solvable smaller-size scheduling problems, whose solutions can be combined for achieving the final schedule. The paper also discusses a number of optimizations that increase the size and compactness of the solvable schedules. We evaluate our approach on a set of realistic large-size multi-hop networks, significantly bigger than those in the existing literature. The results show that our segmentation reduces the synthesis time dramatically, allowing generation of extremely large compact schedules.

Place, publisher, year, edition, pages
Sweden: Mälardalen Real-Time Research Centre, Mälardalen University , 2017.
Series
MRTC Reports, ISSN 1404-3041
Keyword [en]
Real-Time Networks, Scheduling, SMT Solver, Time-Triggered Networks
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-34973ISRN: MDH-MRTC-314/2017-1-SEOAI: oai:DiVA.org:mdh-34973DiVA: diva2:1077629
Projects
RetNet - The European Industrial Doctorate Programme on Future Real-Time Networks
Available from: 2017-02-28 Created: 2017-02-28 Last updated: 2017-03-02Bibliographically approved
In thesis
1. Synthesis of Extremely Large Time-Triggered Network Schedules
Open this publication in new window or tab >>Synthesis of Extremely Large Time-Triggered Network Schedules
2017 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Many embedded systems with real-time requirements demand minimal jitter and low communication end-to-end latency for its communication networks. The time-triggered paradigm, adopted by many real-time protocols, was designed to cope with these demands. A cost-efficient way to implement this paradigm is to synthesize a static schedule that indicates the transmission times of all the time-triggered frames such that all requirements are met. Synthesizing this schedule can be seen as a bin-packing problem, known to be NPcomplete, with complexity driven by the number of frames. In the last years, requirements on the amount of data being transmitted and the scalability of the network have increased. A solution was proposed, adapting real-time switched Ethernet to benefit from its high bandwidth. However, it added more complexity in computing the schedule, since every frame is distributed over multiple links. Tools like Satisfiability Modulo Theory solvers were able to cope with the added complexity and synthesize schedules of industrial size networks. Despite the success of such tools, applications are appearing requiring embedded systems with even more complex networks. In the future, real-time embedded systems, such as large factory automation or smart cities, will need extremely large hybrid networks, combining wired and wireless communication, with schedules that cannot be synthesized with current tools in a reasonable amount of time. With this in mind, the first thesis goal is to identify the performance limits of Satisfiability Modulo Theory solvers in schedule synthesis. Given these limitations, the next step is to define and develop a divide and conquer approach for decomposing the entire scheduling problem in smaller and easy solvable subproblems. However, there are constraints that relate frames from different subproblems. These constraints need to be treated differently and taken into account at the start of every subproblem. The third thesis goal is to develop an approach that is able to synthesize schedules when different frame constraints related to different subproblems are inter-dependent. Last, is to define the requirements that the integration of wireless communication in hybrid networks will bring to the schedule synthesis and how to cope with the increased complexity. We demonstrate the viability of our approaches by means of evaluations, showing that our method is capable to synthesize schedules of hundred of thousands of frames in less than 5 hours.

Place, publisher, year, edition, pages
Västerås: Mälardalen University, 2017
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 255
National Category
Embedded Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-34974 (URN)978-91-7485-314-8 (ISBN)
Presentation
2017-04-06, Gamma, Mälardalens högskola, Västerås, 14:00 (English)
Opponent
Supervisors
Projects
RetNet
Available from: 2017-02-28 Created: 2017-02-28 Last updated: 2017-03-23Bibliographically approved

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