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Buffer-Aware Analysis for Worst-Case Traversal Time of Real-Time Traffic over RRA-based NoCs
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-9736-8490
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1276-3609
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-6132-7945
2017 (English)In: 25th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing PDP'17, 2017Conference paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) is a communication sub-system which has been widely utilized in many-core processors and system-on-chips in general. In order to execute time-critical applications on a NoC-based platform, the timing behavior of the network needs to be predicted during system design. One of the most important timing requirements is regarding schedulability, which refers to determining if a real-time packet can be delivered within a specific time duration. To verify the fulfillment of such timing requirement, a proper timing analysis is mandatory. Our work focuses on a Round-Robin Arbitration (RRA) based wormhole-switched NoC, which is a common architecture used in many of the existing implementations. Recursive Calculus (RC) is one of the existing analysis approaches for RRA-based NoCs which has been utilized in many research works. However, RC does not take buffer-effects into account. As a result, while performing RC on most of the existing RRA-based NoC designs, it can produce unsafe estimates which is not acceptable for time-critical systems. In this paper, we identify the optimistic problem of RC, and we propose a Revised Recursive Calculus (RRC) which extends RC by considering buffer-effects as well as supporting packetization.

Place, publisher, year, edition, pages
2017.
Keyword [en]
Many-CoreNetwork-on-ChipBufferTiming Analysis
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-34101OAI: oai:DiVA.org:mdh-34101DiVA: diva2:1056452
Conference
25th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing PDP'17, 6-8 Mar 2017, Saint-Petersburg, Russian Federation
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and Control
Available from: 2016-12-14 Created: 2016-12-13 Last updated: 2017-03-09Bibliographically approved

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CiteExportLink to record
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  • apa
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