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Period-Aware Segmented Synthesis of Schedules for Multi-Hop Time-Triggered Networks
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1228-5176
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-4987-7669
TTTech Computertechnik AG, Vienna, Austria.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-7235-6888
2016 (English)In: 22nd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2016), IEEE, 2016, 170-175 p.Conference paper (Refereed)
Abstract [en]

Time-triggered offline scheduling is a cost-efficien way to guarantee low communication end-to-end latency and minimal jitter for communication networks in real-time systems. The schedule is generated pre-runtime and indicates the transmission times of time-triggered frames such that contention is prevented. The synthesis of such offline schedules is a bin-packing problem, known to be NP-complete, with complexity driven by the constraints on frame transmissions, and the number of frames in the schedule. Satisfiability Modulo Theories combined with segmented approaches have been successfully used for synthesizing schedules of large networks. However, such synthesis did not take into account frames periods that are much shorter than the time to execute the schedule cycle. This paper presents a periodaware segmented approach that takes into account the frame periods in order to allocate various instances of a frame within a single cycle. We describe three different synthesis strategies and evaluate them with different synthetic experiments. The results show better performance for one of the strategies, which can synthesize schedules of large networks with high communication loads in less than one hour. We also report how the synthesis time and the schedule quality can change with different parameter configurations.

Place, publisher, year, edition, pages
IEEE, 2016. 170-175 p.
Series
IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, ISSN 1533-2306
Keyword [en]
computational complexity, optimization, time-triggered networks
National Category
Embedded Systems
Research subject
Computer Science
Identifiers
URN: urn:nbn:se:mdh:diva-34010DOI: 10.1109/RTCSA.2016.42ISI: 000387085600032OAI: oai:DiVA.org:mdh-34010DiVA: diva2:1051004
Conference
22nd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2016)
Available from: 2016-11-30 Created: 2016-11-30 Last updated: 2017-02-28Bibliographically approved
In thesis
1. Synthesis of Extremely Large Time-Triggered Network Schedules
Open this publication in new window or tab >>Synthesis of Extremely Large Time-Triggered Network Schedules
2017 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Many embedded systems with real-time requirements demand minimal jitter and low communication end-to-end latency for its communication networks. The time-triggered paradigm, adopted by many real-time protocols, was designed to cope with these demands. A cost-efficient way to implement this paradigm is to synthesize a static schedule that indicates the transmission times of all the time-triggered frames such that all requirements are met. Synthesizing this schedule can be seen as a bin-packing problem, known to be NPcomplete, with complexity driven by the number of frames. In the last years, requirements on the amount of data being transmitted and the scalability of the network have increased. A solution was proposed, adapting real-time switched Ethernet to benefit from its high bandwidth. However, it added more complexity in computing the schedule, since every frame is distributed over multiple links. Tools like Satisfiability Modulo Theory solvers were able to cope with the added complexity and synthesize schedules of industrial size networks. Despite the success of such tools, applications are appearing requiring embedded systems with even more complex networks. In the future, real-time embedded systems, such as large factory automation or smart cities, will need extremely large hybrid networks, combining wired and wireless communication, with schedules that cannot be synthesized with current tools in a reasonable amount of time. With this in mind, the first thesis goal is to identify the performance limits of Satisfiability Modulo Theory solvers in schedule synthesis. Given these limitations, the next step is to define and develop a divide and conquer approach for decomposing the entire scheduling problem in smaller and easy solvable subproblems. However, there are constraints that relate frames from different subproblems. These constraints need to be treated differently and taken into account at the start of every subproblem. The third thesis goal is to develop an approach that is able to synthesize schedules when different frame constraints related to different subproblems are inter-dependent. Last, is to define the requirements that the integration of wireless communication in hybrid networks will bring to the schedule synthesis and how to cope with the increased complexity. We demonstrate the viability of our approaches by means of evaluations, showing that our method is capable to synthesize schedules of hundred of thousands of frames in less than 5 hours.

Place, publisher, year, edition, pages
Västerås: Mälardalen University, 2017
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 255
National Category
Embedded Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-34974 (URN)978-91-7485-314-8 (ISBN)
Presentation
2017-04-06, Gamma, Mälardalens högskola, Västerås, 14:00 (English)
Opponent
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RetNet
Available from: 2017-02-28 Created: 2017-02-28 Last updated: 2017-03-23Bibliographically approved

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Citation style
  • apa
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More styles
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