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Using Segmentation to Improve Schedulability of RRA-based NoCs with Mixed Traffic
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-9736-8490
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1276-3609
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-6132-7945
2017 (English)In: 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2017, 744-750 p., 7858413Conference paper, (Refereed)
Abstract [en]

Network-on-Chip (NoC) is the interconnect of choice for many- core processors and system-on-chips in general. Most of the exist- ing NoC designs focus on the performance with respect to average throughput, which makes them less applicable for real-time appli- cations especially when applications have hard timing requirements on the worst-case scenarios. In this paper, we focus on a Round- Robin Arbitration (RRA) based wormhole-switched NoC which is a common architecture used in most of the existing implementa- tions. We propose a novel segmentation algorithm targeting RRA- based NoCs in order to improve the schedulability of real-time traf- fic without modifying the hardware architecture. Additionally, we also address the problem of transmitting both real-time traffic and best-effort traffic in the same NoC. The proposed solutions aim to provide timing guarantees to real-time traffic and achieve low la- tency for best-effort traffic. According to the evaluation results, the proposed segmentation solution can significantly improve the schedulability of the whole network.

Place, publisher, year, edition, pages
2017. 744-750 p., 7858413
Series
Asia and South Pacific Design Automation Conference Proceedings, ISSN 2153-6961
Keyword [en]
Network-on-ChipBest-EffortReal-Time Mixed-Traffic
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-33808DOI: 10.1109/ASPDAC.2017.7858413ISI: 000403609600138Scopus ID: 2-s2.0-85015315749ISBN: 978-1-5090-1558-0 (print)OAI: oai:DiVA.org:mdh-33808DiVA: diva2:1048569
Conference
22nd Asia and South Pacific Design Automation Conference ASP-DAC'17, 16-19 Jan 2017, Chiba / Tokyo, Japan
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and Control
Available from: 2016-11-21 Created: 2016-11-21 Last updated: 2017-07-06Bibliographically approved
In thesis
1. Real-Time Communication over Wormhole-Switched On-Chip Networks
Open this publication in new window or tab >>Real-Time Communication over Wormhole-Switched On-Chip Networks
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In a modern industrial system, the requirement on computational capacity has increased dramatically, in order to support a higher number of functionalities, to process a larger amount of data or to make faster and safer run-time decisions. Instead of using a traditional single-core processor where threads can only be executed sequentially, multi-core and many-core processors are gaining more and more attentions nowadays. In a multi-core processor, software programs can be executed in parallel, which can thus boost the computational performance. Many-core processors are specialized multi-core processors with a larger number of cores which are designed to achieve a higher degree of parallel processing. An on-chip communication bus is a central intersection used for data-exchange between cores, memory and I/O in most multi-core processors. As the number of cores increases, more contention can occur on the communication bus which raises a bottleneck of the overall performance. Therefore, in order to reduce contention incurred on the communication bus, a many-core processor typically employs a Network-on-Chip (NoC) to achieve data-exchange. Real-time embedded systems have been widely utilized for decades. In addition to the correctness of functionalities, timeliness is also an important factor in such systems. Violation of specific timing requirements can result in performance degradation or even fatal problems. While executing real-time applications on many-core processors, the timeliness of a NoC, as a communication subsystem, is essential as well. Unfortunately, many real-time system designs over-provision resources to guarantee the fulfillment of timing requirements, which can lead to significant resource waste. For example, analysis of a NoC design yields that the network is already saturated (i.e. accepting more traffic can incur requirement violation), however, in reality the network actually has the capacity to admit more traffic. In this thesis, we target such resource wasting problems related to design and analysis of NoCs that are used in real-time systems. We propose a number of solutions to improve the schedulability of real-time traffic over wormhole-switched NoCs in order to further improve the resource utilization of the whole system. The solutions focus mainly on two aspects: (1) providing more accurate and efficient time analyses; (2) proposing more cost-effective scheduling methods.

Place, publisher, year, edition, pages
Västerås: Malardalen University Press, 2017
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 232
Keyword
real-time system, network-on-chips
National Category
Embedded Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-35316 (URN)978-91-7485-332-2 (ISBN)
Public defence
2017-06-20, Gamma, Västerås, 09:15 (English)
Opponent
Supervisors
Available from: 2017-05-15 Created: 2017-05-12 Last updated: 2017-07-10Bibliographically approved

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Citation style
  • apa
  • harvard1
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  • modern-language-association-8th-edition
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More styles
Language
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Output format
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