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Using Segmentation to Improve Schedulability of RRA-based NoCs with Mixed Traffic
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-9736-8490
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1276-3609
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-6132-7945
2017 (English)In: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2017, 744-750 p., 7858413Conference paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) is the interconnect of choice for many- core processors and system-on-chips in general. Most of the exist- ing NoC designs focus on the performance with respect to average throughput, which makes them less applicable for real-time appli- cations especially when applications have hard timing requirements on the worst-case scenarios. In this paper, we focus on a Round- Robin Arbitration (RRA) based wormhole-switched NoC which is a common architecture used in most of the existing implementa- tions. We propose a novel segmentation algorithm targeting RRA- based NoCs in order to improve the schedulability of real-time traf- fic without modifying the hardware architecture. Additionally, we also address the problem of transmitting both real-time traffic and best-effort traffic in the same NoC. The proposed solutions aim to provide timing guarantees to real-time traffic and achieve low la- tency for best-effort traffic. According to the evaluation results, the proposed segmentation solution can significantly improve the schedulability of the whole network.

Place, publisher, year, edition, pages
2017. 744-750 p., 7858413
Keyword [en]
Network-on-ChipBest-EffortReal-Time Mixed-Traffic
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-33808DOI: 10.1109/ASPDAC.2017.7858413ScopusID: 2-s2.0-85015315749ISBN: 978-1-5090-1558-0 (print)OAI: oai:DiVA.org:mdh-33808DiVA: diva2:1048569
Conference
22nd Asia and South Pacific Design Automation Conference ASP-DAC'17, 16-19 Jan 2017, Chiba / Tokyo, Japan
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and Control
Available from: 2016-11-21 Created: 2016-11-21 Last updated: 2017-03-30Bibliographically approved

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Liu, MengBecker, MatthiasBehnam, MorisNolte, Thomas
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CiteExportLink to record
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
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More languages
Output format
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  • asciidoc
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