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Synthesizing Job-Level Dependencies for Automotive Multi-Rate Effect Chains
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1276-3609
Research and Technology Centre, Robert Bosch, India.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0003-3242-6113
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
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2016 (English)In: The 22th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'16, 2016, Vol. sept, p. 159-169, article id 579951Conference paper, Published paper (Refereed)
Abstract [en]

Today’s automotive embedded systems comprise a multitude of functionalities, many with complex timing re- quirements. Besides task specific timing requirements, such ap- plications often have timing requirements for the propagation of data through a chain of tasks. An important metric for control applications is the data age, which is addressed in this work. The analysis of such systems is non-trivial because tasks involved in the data propagation may execute at different periods, which leads to over and undersampling within one chain. This work presents a novel method to compute worst- and best-case end-to-end latencies for such systems. A second contribution synthesizes job-level dependencies for such task sets in a way that data paths which exceed the age constraint are eliminated. An extensive evaluation is performed on synthetic task sets and the applicability to industrial applications is demonstrated in a case study.

Place, publisher, year, edition, pages
2016. Vol. sept, p. 159-169, article id 579951
Keywords [en]
End-to-End LatencyCause-Effect ChainAutomotiveAge ConstraintData Age
National Category
Engineering and Technology Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:mdh:diva-32854DOI: 10.1109/RTCSA.2016.41ISI: 000387085600031Scopus ID: 2-s2.0-84994493307OAI: oai:DiVA.org:mdh-32854DiVA, id: diva2:1008985
Conference
The 22th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'16, 17 Aug 2016, Daegu, South Korea
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and ControlAvailable from: 2016-09-30 Created: 2016-08-24 Last updated: 2017-11-02Bibliographically approved
In thesis
1. Consolidating Automotive Real-Time Applications on Many-Core Platforms
Open this publication in new window or tab >>Consolidating Automotive Real-Time Applications on Many-Core Platforms
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Automotive systems have transitioned from basic transportation utilities to sophisticated systems. The rapid increase in functionality comes along with a steep increase in software complexity. This manifests itself in a surge of the number of functionalities as well as the complexity of existing functions. To cope with this transition, current trends shift away from today’s distributed architectures towards integrated architectures, where previously distributed functionality is consolidated on fewer, more powerful, computers. This can ease the integration process, reduce the hardware complexity, and ultimately save costs.

One promising hardware platform for these powerful embedded computers is the many-core processor. A many-core processor hosts a vast number of compute cores, that are partitioned on tiles which are connected by a Network-on-Chip. These natural partitions can provide exclusive execution spaces for different applications, since most resources are not shared among them. Hence, natural building blocks towards temporally and spatially separated execution spaces exist as a result of the hardware architecture.

Additionally to the traditional task local deadlines, automotive applications are often subject to timing constraints on the data propagation through a chain of semantically related tasks. Such requirements pose challenges to the system designer as they are only able to verify them after the system synthesis (i.e. very late in the design process).

In this thesis, we present methods that transform complex timing constraints on the data propagation delay to precedence constraints between individual jobs. An execution framework for the cluster of the many-core is proposed that allows access to cluster external memory while it avoids contention on shared resources by design. A partitioning and configuration of the Network-on-Chip provides isolation between the different applications and reduces the access time from the clusters to external memory. Moreover, methods that facilitate the verification of data propagation delays in each development step are provided. 

Place, publisher, year, edition, pages
Västerås: Malardalen University, 2017
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 246
Keywords
Many-Core, Automotive, Network-on-Chip, Real-Time, Timing analysis
National Category
Embedded Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-37182 (URN)978-91-7485-359-9 (ISBN)
Public defence
2017-12-19, Kappa, Mälardalens högskola, Västerås, 09:00 (English)
Opponent
Supervisors
Available from: 2017-11-06 Created: 2017-11-02 Last updated: 2017-11-27Bibliographically approved

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