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Probabilistic Instruction Cache Analysis using Bayesian Networks
University of York.
University of York.ORCID-id: 0000-0003-2415-8219
2011 (Engelska)Ingår i: Proceedings - 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011, 2011, Vol. 1, s. 233-242Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

Current approaches to instruction cache analysis for determining worst-case execution time rely on building a mathematical model of the cache that tracks its contents at all points in the program. This requires perfect knowledge of the functional behaviour of the cache and may result in extreme complexity and pessimism if many alternative paths through code sections are possible. To overcome these issues, this paper proposes a new hybrid approach in which information obtained from program traces is used to automate the construction of a model of how the cache is used. The resulting model involves the learning of a Bayesian network that predicts which instructions result in cache misses as a function of previously taken paths. The model can then be utilised to predict cache misses for previously unseen inputs and paths. The accuracy of this learned model is assessed against real benchmarks and an established statistical approach to illustrate its benefits.

Ort, förlag, år, upplaga, sidor
2011. Vol. 1, s. 233-242
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Teknik och teknologier
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URN: urn:nbn:se:mdh:diva-23829DOI: 10.1109/RTCSA.2011.55Scopus ID: 2-s2.0-84855558159ISBN: 978-076954502-8 (tryckt)OAI: oai:DiVA.org:mdh-23829DiVA, id: diva2:682482
Konferens
17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011; Toyama; Japan; 28 August 2011 through 31 August 2011
Tillgänglig från: 2013-12-27 Skapad: 2013-12-19 Senast uppdaterad: 2014-05-16Bibliografiskt granskad

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