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Implementing a Clock Synchronization Protocol on a Multi-Master Switched Ethernet Network
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. (IS (Embedded Systems))ORCID-id: 0000-0003-3469-1834
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. (IS (Embedded Systems))ORCID-id: 0000-0002-1687-930X
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Universitat de les Illes Balears, Spain. (IS (Embedded Systems))ORCID-id: 0000-0002-4987-7669
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. (IS (Embedded Systems))ORCID-id: 0000-0001-6132-7945
2013 (Engelska)Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

The interest to use Switched Ethernet technologies in real-time communication is increasing due to its absence of collisions when transmitting messages. Nevertheless, using COTS switches affect the timeliness guarantee inherent in potentially overflowing internal FIFO queues. In this paper we focus on a solution, called the FTT-SE protocol, which is developed based on a master-slave technique. Recently, an extension of the FTT-SE protocol has been proposed where the transmission of messages are controlled using multiple master nodes. In order to guarantee the correctness of the protocol, the masters should be timely synchronized. Therefore, in this paper we investigate using a clock synchronization protocol, based on the IEEE 1588 standard, among master nodes and we study the effects of this protocol on the network performance. In addition, we present a formal verification of this solution by means of model checking to prove the correctness of the FTT-SE protocol when the clock synchronization protocol is applied.

Ort, förlag, år, upplaga, sidor
2013. s. Article number 6647957-
Nationell ämneskategori
Teknik och teknologier
Identifikatorer
URN: urn:nbn:se:mdh:diva-21365DOI: 10.1109/ETFA.2013.6647957Scopus ID: 2-s2.0-84890679568ISBN: 9781479908622 (tryckt)OAI: oai:DiVA.org:mdh-21365DiVA, id: diva2:649008
Konferens
18th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA13), 10-13 September 2013, Cagliari, Italy
Projekt
PRESS - Predictable Embedded Software SystemsTillgänglig från: 2013-09-17 Skapad: 2013-09-11 Senast uppdaterad: 2016-11-01Bibliografiskt granskad
Ingår i avhandling
1. Multi-Hop Real-Time Communication over Switched Ethernet Technology
Öppna denna publikation i ny flik eller fönster >>Multi-Hop Real-Time Communication over Switched Ethernet Technology
2014 (Engelska)Licentiatavhandling, sammanläggning (Övrigt vetenskapligt)
Abstract [en]

Switched Ethernet technology has been introduced to be exploited in real-time communication systems due to its features such as its high throughput and wide availability, hence being a cost-effective solution. Many real-time switched Ethernet protocols have been developed, preserving the profits of traditional Ethernet technology, to overcome the limitations imposed by using commercially available (COTS) switches. These limitations mainly originate from the non-deterministic behavior of the Ethernet switches inherent in the use of FIFO queues and a limited number of priority levels.

 

In our research we focus on two particular real-time communication technologies, one based on COTS Ethernet switches named the FTT-SE architecture and the other using a modified Ethernet switch called the HaRTES architecture. Both architectures are based on a master-slave technique supporting different and temporally isolated traffic types including real-time periodic, real-time sporadic and non-real-time traffic. Also, they provide mechanisms implementing adaptivity as a response to the requirements imposed by dynamic real-time applications. Nevertheless, the two mentioned architectures were originally developed for a simple network consisting of a single switch, and they were lacking support for multi-hop communication. In industrial applications, multi-hop communication is essential as the networks comprise a high number of nodes, that is far beyond the capability of a single switch.

 

In this thesis, we study the challenges of building multi-hop communication using the FTT-SE and the HaRTES architectures. We propose different architectures to provide multi-hop communication while preserving the key characteristics of the single-switch architecture such as timeliness guarantee, resource efficiency, adaptivity and dynamicity. We develop a response time analysis for each proposed architecture and we compare them to assess their corresponding benefits and limitations. Further, we develop a simulation tool to evaluate the solutions.

Ort, förlag, år, upplaga, sidor
Västerås: Mälardalen University, 2014
Serie
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 184
Nationell ämneskategori
Inbäddad systemteknik Kommunikationssystem
Forskningsämne
datavetenskap
Identifikatorer
urn:nbn:se:mdh:diva-26121 (URN)978-91-7485-168-7 (ISBN)
Presentation
2014-11-18, Delta, Mälardalens högskola, Västerås, 13:30 (Engelska)
Opponent
Handledare
Tillgänglig från: 2014-10-20 Skapad: 2014-10-17 Senast uppdaterad: 2014-11-12Bibliografiskt granskad

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