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APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors
Tallinn University of Technology, Estonia.
Tallinn University of Technology, Estonia.
Tallinn University of Technology, Estonia.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Tallinn University of Technology, Estonia.
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2023 (English)In: Proceedings - 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Institute of Electrical and Electronics Engineers Inc. , 2023, p. 124-127Conference paper, Published paper (Refereed)
Abstract [en]

Nowadays, the extensive exploitation of Deep Neural Networks (DNNs) in safety-critical applications raises new reliability concerns. In practice, methods for fault injection by emulation in hardware are efficient and widely used to study the resilience of DNN architectures for mitigating reliability issues already at the early design stages. However, the state-of-the-art methods for fault injection by emulation incur a spectrum of time-, design-and control-complexity problems. To overcome these issues, a novel resiliency assessment method called APPRAISER is proposed that applies functional approximation for a non-conventional purpose and employs approximate computing errors for its interest. By adopting this concept in the resiliency assessment domain, APPRAISER provides thousands of times speed-up in the assessment process, while keeping high accuracy of the analysis. In this paper, APPRAISER is validated by comparing it with state-of-the-art approaches for fault injection by emulation in FPGA. By this, the feasibility of the idea is demonstrated, and a new perspective in resiliency evaluation for DNNs is opened.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc. , 2023. p. 124-127
Keywords [en]
approximate computing, Deep Neural Networks, fault injection, reliability, resiliency assessment, Reliability analysis, Safety engineering, Software testing, Approximation errors, Early design stages, Fault resilience, Network faults, Neural network architecture, Safety critical applications, State-of-the-art methods
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-63672DOI: 10.1109/DDECS57882.2023.10139468ISI: 001012062000024Scopus ID: 2-s2.0-85161915380ISBN: 9798350332773 (print)OAI: oai:DiVA.org:mdh-63672DiVA, id: diva2:1776840
Conference
26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, 3-5 May 2023, Tallin, Estonia
Available from: 2023-06-28 Created: 2023-06-28 Last updated: 2023-12-04Bibliographically approved

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Daneshtalab, Masoud

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