https://www.mdu.se/

mdu.sePublications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Network Calculus Approach for Packet Delay Variation Analysis of Multi-Hop Wired Networks
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-6942-4229
Mälardalen University, School of Innovation, Design and Engineering, Innovation and Product Realisation.ORCID iD: 0000-0003-2018-0996
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-7159-7508
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-2419-2735
2022 (English)In: Applied Sciences, E-ISSN 2076-3417, Vol. 12, no 21, article id 11207Article in journal (Refereed) Published
Abstract [en]

The Industrial Internet of Things (IIoT) has revolutionized businesses by changing the way data are used to make products and services more efficient, reliable, and profitable. To achieve the improvement goals, the IIoT must guarantee the real-time performance of industrial applications such as motion control, by providing stringent quality of service (QoS) assurances for their (industrial applications) communication networks. An application or service may malfunction without adequate network QoS, resulting in potential product failures. Since an acceptable end-to-end delay and low jitter or packet delay variation (PDV) are closely related to quality of service (QoS), their impact is significant in ensuring the real-time performance of industrial applications. Although a communication network topology ensures certain jitter levels, its real-life performance is affected by dynamic traffic due to the changing number of devices, services, and applications present in the communication network. Hence, it is essential to study the jitter experienced by real-time traffic in the presence of background traffic and how it can be maintained within the limits to ensure a certain level of QoS. This paper presents a probabilistic network calculus approach that uses moment-generating functions to analyze the delay and PDV incurred by the traffic flows of interest in a wired packet switched multi-stage network. The presented work derives closed-form, end-to-end, probabilistic performance bounds for delay and PDV for several servers in series in the presence of background traffic. The PDV analysis conducted with the help of a Markovian traffic model for background traffic showed that the parameters from the background traffic significantly impact PDV and that PDV can be maintained under the limits by controlling the shape of the background traffic. For the studied configurations, the model parameters can change the PDV bound from 1 ms to 100 ms. The results indicated the possibility of using the model parameters as a shaper of the background traffic. Thus, the analysis can be beneficial in providing QoS assurances for real-time applications.

Place, publisher, year, edition, pages
MDPI , 2022. Vol. 12, no 21, article id 11207
Keywords [en]
packet delay variation, jitter, QoS, packet delay, moment-generating functions, network calculus, Markovian on-off model
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:mdh:diva-61059DOI: 10.3390/app122111207ISI: 000883357900001Scopus ID: 2-s2.0-85141832712OAI: oai:DiVA.org:mdh-61059DiVA, id: diva2:1714582
Available from: 2022-11-30 Created: 2022-11-30 Last updated: 2023-10-06Bibliographically approved
In thesis
1. Improving Clock Synchronization Performance in Industrial Networks
Open this publication in new window or tab >>Improving Clock Synchronization Performance in Industrial Networks
2023 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The recent advances in cyber-physical systems and industrial internet-of-things (IIoT) have enabled the convergence of information technology (IT) and operational technology (OT) worlds of industrial automation systems achieving higher productivity, reliability, and revenues. The availability of business-critical and production-critical data on the converged network has enabled new and advanced network-centric applications that require time-constrained embedded devices to be connected to “the internet.'' The massively interconnected IIoT devices communicating in real-time require a accurate, scalable, easy-to-deploy, and cost-effective clock synchronization service for the ordering of information collected throughout a network. Thus, a time or clock synchronization service that aligns the devices' clocks in the network to ensure accurate timestamping and orderly event executions, has gained great importance. The industrial networks are heterogeneous in nature, where various grades of hardware resources along with varied software complexities operate in average to extremely harsh and hostile environments. The heterogeneity and the huge number of devices make it challenging to achieve an adequate level of clock synchronization in industrial networks with existing hardware and software-based solutions. For this reason, the thesis aims to enhance the accuracy of the most-economical, highly scalable, and easy-to-deploy software-based clock synchronization in wired industrial networks with the hypothesis that predictive software strategies can compensate for their lack of accuracy.

The first step towards this goal is to identify the industrial network characteristics essential for improving clock synchronization. The analysis of real network data from an industrial site confirmed that packet delay variation (PDV) could assure the clock synchronization performance in an industrial network. Using signal processing-based PDV compensation methods, we propose enhanced clock synchronization algorithms, namely, 'CoSiNeT' and 'CoSiWiNet' for local and wide area industrial networks. Based on the analysis in real networks, both algorithms outperform state-of-the-practice and state-of-the-art methods in degrading network scenarios. Once the significance of PDV in synchronization performance has been confirmed, the next step is identifying the network parameters significantly affecting PDV. The thesis provides a network calculus-based PDV analysis of synchronization messages in a multi-stage wired packet-switched network under the presence of stochastic  background traffic. The analysis, based on a closed-form, end-to-end probabilistic analytical model of PDV, identifies the network parameters that significantly affect PDV. It further unveils the significant relationship between PDV incurred by synchronization messages and the rate, burstiness of background network traffic parameters. Bounding the PDV or jitter under a certain level can be beneficial for applications such as synchronization, where PDV is a significant decider of assured performance. A Sigma traffic shaper is proposed to maintain PDV under limits by controlling the rate of incoming background traffic at the ingress port of the network. We further estimate the probability of a synchronization message loss due to the shaper, given the finite buffers available at network stages. The loss probability estimation is a vital trade-off tool that can be utilized to fix the limiting rate for a desired PDV maintenance. Finally, we extend the PDV analysis to predict the probabilistic clock synchronization accuracy bound for given network conditions. The performance analysis conducted with proposed configurations showed that limiting the arrival traffic rate to 50% resulted in PDV levels and in turn synchronization accuracy being reduced from a few milliseconds to a few microseconds.

Place, publisher, year, edition, pages
Västerås: Mälardalen university, 2023
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 389
Keywords
Clock synchronization, Industrial networks, Internet of things, Industry 4.0, Network Calculus
National Category
Computer Sciences
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-64472 (URN)978-91-7485-612-5 (ISBN)
Public defence
2023-11-28, Kappa, Mälardalens universitet, Västerås, 14:15 (English)
Opponent
Supervisors
Available from: 2023-10-09 Created: 2023-10-06 Last updated: 2023-11-07Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Authority records

Gore, Rahul NandkumarLisova, ElenaÅkerberg, JohanBjörkman, Mats

Search in DiVA

By author/editor
Gore, Rahul NandkumarLisova, ElenaÅkerberg, JohanBjörkman, Mats
By organisation
Embedded SystemsInnovation and Product Realisation
In the same journal
Applied Sciences
Computer Sciences

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 28 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf