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AutoDeepHLS: Deep Neural Network High-level Synthesis using fixed-point precision
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-7586-0409
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-5297-6548
2022 (English)In: 2022 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2022): INTELLIGENT TECHNOLOGY IN THE POST-PANDEMIC ERA, IEEE , 2022, p. 122-125Conference paper, Published paper (Refereed)
Abstract [en]

Deep Neural Networks (DNN) have received much attention in various applications such as visual recognition, self-driving cars, health care, etc. Hardware implementation, specifically using FPGA and ASIC due to their high performance and low power consumption, is considered an efficient method. However, implementation on these platforms is difficult for neural network designers since they usually have limited knowledge of hardware. High-Level Synthesis (HLS) tools can act as a bridge between high-level DNN designs and hardware implementation. Nevertheless, these tools usually need implementation at the C level, whereas the design of neural networks is usually performed at a higher level (such as Keras or TensorFlow). In this paper, we propose a fully automated flow for creating a C-level implementation that is synthesizable with HLS Tools. Various aspects such as performance, minimal access to memory elements, data type knobs, and design verification are considered. Our results show that the generated C implementation is much more HLS friendly than previous works. Furthermore, a complete flow is proposed to determine different fixed-point precisions for network elements. We show that our method results in 25% and 34% reduction in bit-width for LeNet and VGG, respectively, without any accuracy loss.

Place, publisher, year, edition, pages
IEEE , 2022. p. 122-125
Keywords [en]
Deep Neural Network, Accelerator, High-Level Synthesis, Fixed-Point, Quantization
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-60590DOI: 10.1109/AICAS54282.2022.9869907ISI: 000859273200032Scopus ID: 2-s2.0-85139073458ISBN: 978-1-6654-0996-4 (print)OAI: oai:DiVA.org:mdh-60590DiVA, id: diva2:1709526
Conference
IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) - Intelligent Technology in the Post-Pandemic Era, JUN 13-15, 2022, Incheon, SOUTH KOREA
Available from: 2022-11-09 Created: 2022-11-09 Last updated: 2023-10-09Bibliographically approved
In thesis
1. DeepKit: a multistage exploration framework for hardware implementation of deep learning
Open this publication in new window or tab >>DeepKit: a multistage exploration framework for hardware implementation of deep learning
2023 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Deep Neural Networks (DNNs) are widely adopted to solve different problems ranging from speech recognition to image classification. DNNs demand a large amount of processing power, and their implementation on hardware, i.e., FPGA or ASIC, has received much attention. However, it is impossible to implement a DNN on hardware directly from its DNN descriptions, usually in Python language, libraries, and APIs. Therefore, it should be either implemented from scratch at Register Transfer Level (RTL), e.g., in VHDL or Verilog, or be transformed to a lower level implementation. One idea that has been recently considered is converting a DNN to C and then using High-Level Synthesis (HLS) to synthesize it on an FPGA. Nevertheless, there are various aspects to take into consideration during the transformation. In this thesis, we propose a multistage framework, DeepKit, that generates a synthesizable C implementation based on an input DNN architecture in a DNN description (Keras). Then, moving through the stages, various explorations and optimizations are performed with regard to accuracy, latency, resource utilization, and reliability. The framework is also implemented as a toolchain consisting of DeepHLS, AutoDeepHLS, DeepAxe, and DeepFlexiHLS, and results are provided for DNNs of various types and sizes.

Place, publisher, year, edition, pages
Västerås: Mälardalen university, 2023
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 390
National Category
Embedded Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-64488 (URN)978-91-7485-613-2 (ISBN)
Public defence
2023-12-07, Delta, Mälardalens universitet, Västerås, 13:00 (English)
Opponent
Supervisors
Available from: 2023-10-09 Created: 2023-10-09 Last updated: 2023-11-16Bibliographically approved

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Riazati, MohammadDaneshtalab, MasoudSjödin, MikaelLisper, Björn

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