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Automated test mapping and coverage for network topologies
Westermo RandD AB, Sweden.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1660-199X
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-5032-2310
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2018 (English)In: ISSTA 2018 - Proceedings of the 27th ACM SIGSOFT International Symposium on Software Testing and Analysis, Association for Computing Machinery, Inc , 2018, p. 73-83Conference paper, Published paper (Refereed)
Abstract [en]

Communication devices such as routers and switches play a critical role in the reliable functioning of embedded system networks. Dozens of such devices may be part of an embedded system network, and they need to be tested in conjunction with various computational elements on actual hardware, in many different configurations that are representative of actual operating networks. An individual physical network topology can be used as the basis for a test system that can execute many test cases, by identifying the part of the physical network topology that corresponds to the configuration required by each individual test case. Given a set of available test systems and a large number of test cases, the problem is to determine for each test case, which of the test systems are suitable for executing the test case, and to provide the mapping that associates the test case elements (the logical network topology) with the appropriate elements of the test system (the physical network topology). We studied a real industrial environment where this problem was originally handled by a simple software procedure that was very slow in many cases, and also failed to provide thorough coverage of each network's elements. In this paper, we represent both the test systems and the test cases as graphs, and develop a new prototype algorithm that a) determines whether or not a test case can be mapped to a subgraph of the test system, b) rapidly finds mappings that do exist, and c) exercises diverse sets of network nodes when multiple mappings exist for the test case. The prototype has been implemented and applied to over 10,000 combinations of test cases and test systems, and reduced the computation time by a factor of more than 80 from the original procedure. In addition, relative to a meaningful measure of network topology coverage, the mappings achieved an increased level of thoroughness in exercising the elements of each test system.

Place, publisher, year, edition, pages
Association for Computing Machinery, Inc , 2018. p. 73-83
Keywords [en]
Network topology, Subgraph isomorphism, Test coverage, Testing, Embedded systems, Mapping, Test facilities, Topology, Communication device, Computational elements, Industrial environments, Physical network topologies, Prototype algorithms, Software testing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:mdh:diva-40528DOI: 10.1145/3213846.3213859Scopus ID: 2-s2.0-85051515196ISBN: 9781450356992 (print)OAI: oai:DiVA.org:mdh-40528DiVA, id: diva2:1241246
Conference
27th ACM SIGSOFT International Symposium on Software Testing and Analysis, ISSTA 2018, 16 July 2018 through 21 July 2018
Available from: 2018-08-23 Created: 2018-08-23 Last updated: 2018-10-02Bibliographically approved
In thesis
1. Automated System Level Software Testing of Networked Embedded Systems
Open this publication in new window or tab >>Automated System Level Software Testing of Networked Embedded Systems
2018 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Embedded systems are ubiquitous and play critical roles in management systems for industry and transport. Software failures in these domains may lead to loss of production or even loss of life, so the software in these systems needs to be reliable. Software testing is a standard approach for quality assurance of embedded software, and many software development processes strive for test automation. However, important challenges for successful software test automation are: lack of time for testing, lack of test environment availability, and an excess of test results information that renders decision-making hard.

In this thesis these challenges are tackled in three ways. First, in order to combat lack of time for testing, a method for automated system level regression test selection was implemented and evaluated using data from several years of nightly testing in a real world industrial setting. It was shown that automated test selection can be integrated into system level nightly testing and solve problems such as nightly testing not finishing on time. Second, in order to improve the hardware coverage of devices in the test environment and how test cases map to hardware, an algorithm based on the subgraph isomorphism problem was implemented and evaluated using industrial data. This implementation was significantly faster than the previous implementation, and the mapping process was done in such a way that hardware coverage increased over iterations. Third, to better understand decision-making in critical steps of the software development process in an industrial setting, two empirical studies were conducted. The results showed how visualizations and a test results database support decision-making. Results also describe the overall flow of information in software testing: from developers to hardware, and back to developers via the test results database.

Automated system level software testing of networked embedded systems can be difficult to achieve. This thesis addresses several important challenges and provides results that are of interest both to industrial practitioners and researchers.

Place, publisher, year, edition, pages
Västerås: Mälardalen University, 2018
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 275
National Category
Software Engineering
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-41109 (URN)978-91-7485-408-4 (ISBN)
Presentation
2018-11-13, Room Zeta, Mälardalens högskola, Västerås, 13:15 (English)
Opponent
Supervisors
Available from: 2018-10-02 Created: 2018-10-02 Last updated: 2018-10-09Bibliographically approved

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Ostrand, Thomas J.WEYUKER, ELAINEDaniel, SundmarkAfzal, Wasif

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