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A novel 18 GHz 1.3 mW CMOS frequency divider with high input sensitivity
Mälardalen University, Department of Computer Science and Electronics.
Mälardalen University, Department of Computer Science and Electronics.
2005 (English)In: ISSCS 2005: International Symposium on Signals, Circuits and Systems - Proceedings, 2005, p. 409-412Conference paper, Published paper (Other academic)
Abstract [en]

A novel CMOS high speed divide-by-two circuit with very low power consumption is proposed in this paper. The circuit features very low input capacitance and a wide locking range of 1.5-18 GHz with a power consumption of less than 13 mW at 1.8 V. The input sensitivity of the stage is improved significantly when compared to conventional dynamic loaded high frequency dividers. The concept and design issue of the circuit is presented together with a performance comparison to existing topologies. The idea is demonstrated and verified in a standard 0.18 μm CMOS process through realistic simulations originating from a complete layout using moderately extracted parasitics.

Place, publisher, year, edition, pages
2005. p. 409-412
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:mdh:diva-4242DOI: 10.1109/ISSCS.2005.1511264ISI: 000231532900103Scopus ID: 2-s2.0-33749043635ISBN: 9780780390294 (print)OAI: oai:DiVA.org:mdh-4242DiVA, id: diva2:121531
Conference
ISSCS 2005: International Symposium on Signals, Circuits and Systems; Iasi; Romania; 14 July 2005 through 15 July 2005
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2018-08-22Bibliographically approved
In thesis
1. Analysis and Design of Low-Phase-Noise Integrated Voltage-Controlled Oscillators for Wide-Band RF Front-Ends
Open this publication in new window or tab >>Analysis and Design of Low-Phase-Noise Integrated Voltage-Controlled Oscillators for Wide-Band RF Front-Ends
2006 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The explosive development of wireless communication services creates a demand for more flexible and cost-effective communication systems that offer higher data rates. The obvious trend towards small-size and ultra low power systems, in combination with the ever increasing number of applications integrated in a single portable device, tightens the design constraints at hardware and software level. The integration of current mobile systems with the third generation systems exemplifies and emphasizes the need of monolithic multi-band transceivers. A long term goal is a software defined radio, where several communication standards and applications are embedded and reconfigured by software. This motivates the need for highly flexible and reconfigurable analog radio frequency (RF) circuits that can be fully integrated in standard low-cost complementary metal-oxide-semiconductor (CMOS) technologies.

In this thesis, the Voltage-Controlled Oscillator (VCO), one of the main challenging RF circuits within a transceiver, is investigated for today’s and future communication systems. The contributions from this work may be divided into two parts. The first part exploits the possibility and design related issues of wide-band reconfigurable integrated VCOs in CMOS technologies. Aspects such as frequency tuning, power dissipation and phase noise performance are studied and design oriented techniques for wide-band circuit solutions are proposed. For demonstration of these investigations several fully functional wide-band multi-GHz VCOs are implemented and characterized in a 0.18µm CMOS technology.

The second part of the thesis concerns theoretical analysis of phase noise in VCOs. Due to the complex process of conversion from component noise to phase noise, computer aided methods or advanced circuit simulators are usually used for evaluation and prediction of phase noise. As a consequence, the fundamental properties of different noise sources and their impact on phase noise in commonly adopted VCO topologies have so far not been completely described. This in turn makes the optimization process of integrated VCOs a very complex task. To aid the design and to provide a deeper understanding of the phase noise mechanism, a new approach based on a linear time-variant model is proposed in this work. The theory allows for derivation of analytic expressions for phase noise, thereby, providing excellent insight on how to minimize and optimize phase noise in oscillators as a function of circuit related parameters. Moreover, it enables a fair performance comparison of different oscillator topologies in order to ascertain which structure is most suitable depending on the application of interest. The proposed method is verified with very good agreement against both advanced circuit simulations and measurements in CMOS and bipolar technologies. As a final contribution, using the knowledge gained from the theoretical analysis, a fully integrated 0.35µm CMOS VCO with superior phase noise performance and power dissipation is demonstrated.

Place, publisher, year, edition, pages
Västerås: Institutionen för Datavetenskap och Elektronik, 2006. p. 166
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 25
Keywords
Electronic
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Elektronik
Identifiers
urn:nbn:se:mdh:diva-88 (URN)91–85485–05-5 (ISBN)
Public defence
2006-01-27, Beta, 14:00
Opponent
Supervisors
Available from: 2006-01-01 Created: 2006-01-01

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