Open this publication in new window or tab >>2004 (English)In: Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3 2004, 2004, p. 217-220Conference paper, Published paper (Other academic)
Abstract [en]
In this paper, we present a new digit-serial hybrid adder. The adder can be pipelined to the bit-level and is, therefore, well suited for high-speed applications. The main advantage of the proposed adder is that it can be implemented with few pipelining stages. We compare speed, area and power consumption for the proposed adder with a digit-serial carry-look-ahead adder and a digit-serial Ladner-Fisher adder. The results show that the delay of the digit-serial hybrid adder is lower than the other adders studied in this paper for digit-sizes up to d = 12. For these digit-sizes the digit-serial hybrid adder has on average 17% smaller critical path than the digit-serial carry-look-ahead adder and 21% smaller critical path than the digit-serial Ladner-Fisher adder.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4017 (URN)10.1109/ISCAS.2004.1328722 (DOI)2-s2.0-4344682862 (Scopus ID)0-7803-8251-X (ISBN)
Conference
2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004
2006-09-062006-09-062015-07-28Bibliographically approved