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Improved Message Forwarding for Multi-Hop HaRTES Real-Time Ethernet Networks
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. MRTC Malardalen Univ, Vasteras, Sweden..ORCID-id: 0000-0003-3469-1834
DETI IT Univ Aveiro, Aveiro, Portugal..
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. MRTC Malardalen Univ, Vasteras, Sweden..ORCID-id: 0000-0002-1687-930X
DETI IT Univ Aveiro, Aveiro, Portugal..
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2016 (Engelska)Ingår i: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115, Vol. 84, nr 1, s. 47-67Artikel i tidskrift (Refereegranskat) Published
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Abstract [en]

Nowadays, switched Ethernet networks are used in complex systems that encompass tens to hundreds of nodes and thousands of signals. Such scenarios require multi-switch architectures where communications frequently occur in multiple hops. In this paper we investigate techniques to allow efficient multi-hop communication using HaRTES switches. These are modified Ethernet switches that provide real-time traffic scheduling, dynamic bandwidth management and temporal isolation between real-time and non-real-time traffic. This paper addresses the problem of forwarding traffic in HaRTES networks. Two methods have been recently proposed, namely Distributed Global Scheduling (DGS) that buffers traffic between switches, and Reduced Buffering Scheme (RBS), that uses immediate forwarding. In this paper, we discuss the design and implementation of RBS within HaRTES and we carry out an experimental validation with a prototype implementation. Then, we carry out a comparison between RBS and DGS using worst-case response time analysis and simulation. The comparison clearly establishes the superiority of RBS concerning end-to-end response times. In fact, with sample message sets, we achieved reductions in end-to-end delay that were as high as 80 %.

Ort, förlag, år, upplaga, sidor
2016. Vol. 84, nr 1, s. 47-67
Nyckelord [en]
Switched Ethernet, HaRTES architecture, Real-time communication, Real-time Ethernet, Response time analysis, Simulation
Nationell ämneskategori
Elektroteknik och elektronik
Identifikatorer
URN: urn:nbn:se:mdh:diva-32178DOI: 10.1007/s11265-015-1010-8ISI: 000376617700004Scopus ID: 2-s2.0-84929118870OAI: oai:DiVA.org:mdh-32178DiVA, id: diva2:941885
Tillgänglig från: 2016-06-23 Skapad: 2016-06-23 Senast uppdaterad: 2017-11-28Bibliografiskt granskad

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