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With the CMOS technology scaling, transistor aging has become one major issue affecting circuit reliability and lifetime. There are two major classes of existing studies that model the aging effects in the circuit delay. One is at transistor-level, which is highly accurate but very slow. The other is at gate-level, which is faster but less accurate. Moreover, most prior studies only consider a limited subset or limited value ranges of aging factors. In this paper, we propose Aadam, a fast, accurate, and versatile aging-aware delay model for generic cell libraries. In Aadam, we first use transistor-level SPICE simulations to accurately characterize the delay degradation of each library cell under a versatile set of aging factors, including both physical parameters (i.e., initial threshold voltage and transistor width/length ratio) and operating conditions (i.e., working temperature, signal probability, input signal slew range, output load capacitance range, and projected lifetime). For each library cell, we then train a feed-forward neural network (FFNN) to learn the relation between the input aging factors and output cell delay degradation. Therefore, for a given input circuit and a given combination of aging factors, we can use the trained FFNNs to quickly and accurately infer the delay degradation for each gate in the circuit. Finally, to effectively estimate the aging-aware lifetime delay of large-scale circuits, we also integrate Aadam into a state-of-the-art static timing analysis tool called OpenTimer. Experimental results demonstrate that Aadam achieves fast estimation of the aging-induced delay with high accuracy close to transistor-level simulation.