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Automatic Generation of Timing Models for Timing Analysis of High-Level Code
University of Applied Sciences Darmstadt, Germany.
Mälardalens högskola, Akademin för innovation, design och teknik.
Mälardalens högskola, Akademin för innovation, design och teknik.ORCID-id: 0000-0001-5297-6548
Mälardalens högskola, Akademin för innovation, design och teknik.ORCID-id: 0000-0001-6571-0175
2011 (engelsk)Inngår i: 19th International Conference on Real-Time and Network Systems (RTNS2011), 2011Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Traditional timing analysis is applied only in the late stages of embedded system software development, when the hardware is available and the code is compiled and linked. However, preliminary timing estimates are often needed already in early stages of system development, both for hard and soft real-time systems. If the hardware is not yet fully accessible, or the code is not yet ready to compile or link, then the timing estimation must be done for the source code rather than for the binary. This paper describes how source-level timing models can be derived automatically for given combinations of hardware architecture and compiler. The models are identified from measured execution times for a set of synthetic "training programs" compiled for the hardware platform in question. The models can be used to derive source-level WCET estimates, as well as for estimating the execution times for single program runs. Our experiments indicate that the models can predict the execution times of the final, compiled code with a deviation up to 20%.

sted, utgiver, år, opplag, sider
2011.
HSV kategori
Identifikatorer
URN: urn:nbn:se:mdh:diva-13592OAI: oai:DiVA.org:mdh-13592DiVA, id: diva2:466135
Konferanse
19th International Conference on Real-Time and Network Systems (RTNS 2011), Nantes, France (Sepember 2011)
Tilgjengelig fra: 2011-12-15 Laget: 2011-12-15 Sist oppdatert: 2015-07-31bibliografisk kontrollert

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Lisper, BjörnGustafsson, Jan

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