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Design challenges in hardware development of time-sensitive networking: A research plan
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.ORCID-id: 0000-0003-3469-1834
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
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2019 (engelsk)Inngår i: CEUR Workshop Proceedings, Volume 2457, CEUR-WS , 2019, Vol. 2457Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Time-Sensitive Networking (TSN) is a set of ongoing projects within the IEEE standardization to guarantee timeliness and low-latency communication based on switched Ethernet for industrial applications. The huge demand is mainly coming from industries where intensive data transmission is required, such as in the modern vehicles where cameras, lidars and high-bandwidth modern sensors are connected. The TSN standards are evolving over time, hence the hardware needs to change depending upon the modifications. In addition, high performance hardware is required to obtain a full benefit from the standards. In this paper, we present a research plan for developing novel techniques to support a parameterized and modular hardware IP core of the multi-stage TSN switch fabric in VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL), which can be deployed in any Field-Programmable-Gate-Array (FPGA) devices. We present the challenges on the way towards the mentioned goal. 

sted, utgiver, år, opplag, sider
CEUR-WS , 2019. Vol. 2457
Serie
CEUR Workshop Proceedings, ISSN 1613-0073 ; 2457
Emneord [en]
FPGA, Memory management, Predictability, Time-sensitive network, Cyber Physical System, Embedded systems, Field programmable gate arrays (FPGA), Integrated circuit design, Vehicle transmissions, Design challenges, Hardware development, High-performance hardware, Low-latency communication, Switched ethernet, Very high speed integrated circuits, Computer hardware description languages
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Identifikatorer
URN: urn:nbn:se:mdh:diva-45837Scopus ID: 2-s2.0-85073187187OAI: oai:DiVA.org:mdh-45837DiVA, id: diva2:1365516
Konferanse
2019 Cyber-Physical Systems PhD Workshop, CPSWS 2019; Alghero; Italy; 23 September 2019
Tilgjengelig fra: 2019-10-25 Laget: 2019-10-25 Sist oppdatert: 2019-12-18bibliografisk kontrollert

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Ghaderi, AdnanDaneshtalab, MasoudAshjaei, Seyed Mohammad HosseinLoni, MohammadMubeen, SaadSjödin, Mikael

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