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Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.ORCID-id: 0000-0002-1276-3609
Technische Universität Braunschweig, Germany.
Robert Bosch GmbH, Renningen, Germany.
CISTER/INESC-TEC, ISEP, Portugal.
Vise andre og tillknytning
2017 (engelsk)Inngår i: 23rd IEEE Real-Time and Embedded Technology and Applications Symposium RTAS'17, 2017, s. 101-112Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip, which is used for communication among the compute cores via the off- chip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms. In this work, we target a state-of-the-art many-core processor, the Kalray MPPA R . A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis.

sted, utgiver, år, opplag, sider
2017. s. 101-112
Emneord [en]
Many-CoreNetwork-on-ChipPartitioningReal-TimeMemory Access
HSV kategori
Identifikatorer
URN: urn:nbn:se:mdh:diva-35460DOI: 10.1109/RTAS.2017.32ISI: 000411195100009Scopus ID: 2-s2.0-85021824983ISBN: 978-1-5090-5269-1 (digital)OAI: oai:DiVA.org:mdh-35460DiVA, id: diva2:1108237
Konferanse
23rd IEEE Real-Time and Embedded Technology and Applications Symposium RTAS'17, 18-21 Apr 2017, Pittsburgh PA, United States
Prosjekter
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and ControlTilgjengelig fra: 2017-06-12 Laget: 2017-06-12 Sist oppdatert: 2017-11-02bibliografisk kontrollert
Inngår i avhandling
1. Consolidating Automotive Real-Time Applications on Many-Core Platforms
Åpne denne publikasjonen i ny fane eller vindu >>Consolidating Automotive Real-Time Applications on Many-Core Platforms
2017 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

Automotive systems have transitioned from basic transportation utilities to sophisticated systems. The rapid increase in functionality comes along with a steep increase in software complexity. This manifests itself in a surge of the number of functionalities as well as the complexity of existing functions. To cope with this transition, current trends shift away from today’s distributed architectures towards integrated architectures, where previously distributed functionality is consolidated on fewer, more powerful, computers. This can ease the integration process, reduce the hardware complexity, and ultimately save costs.

One promising hardware platform for these powerful embedded computers is the many-core processor. A many-core processor hosts a vast number of compute cores, that are partitioned on tiles which are connected by a Network-on-Chip. These natural partitions can provide exclusive execution spaces for different applications, since most resources are not shared among them. Hence, natural building blocks towards temporally and spatially separated execution spaces exist as a result of the hardware architecture.

Additionally to the traditional task local deadlines, automotive applications are often subject to timing constraints on the data propagation through a chain of semantically related tasks. Such requirements pose challenges to the system designer as they are only able to verify them after the system synthesis (i.e. very late in the design process).

In this thesis, we present methods that transform complex timing constraints on the data propagation delay to precedence constraints between individual jobs. An execution framework for the cluster of the many-core is proposed that allows access to cluster external memory while it avoids contention on shared resources by design. A partitioning and configuration of the Network-on-Chip provides isolation between the different applications and reduces the access time from the clusters to external memory. Moreover, methods that facilitate the verification of data propagation delays in each development step are provided. 

sted, utgiver, år, opplag, sider
Västerås: Malardalen University, 2017
Serie
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 246
Emneord
Many-Core, Automotive, Network-on-Chip, Real-Time, Timing analysis
HSV kategori
Forskningsprogram
datavetenskap
Identifikatorer
urn:nbn:se:mdh:diva-37182 (URN)978-91-7485-359-9 (ISBN)
Disputas
2017-12-19, Kappa, Mälardalens högskola, Västerås, 09:00 (engelsk)
Opponent
Veileder
Tilgjengelig fra: 2017-11-06 Laget: 2017-11-02 Sist oppdatert: 2017-11-27bibliografisk kontrollert

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