mdh.sePublikasjoner
Endre søk
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
Buffer-Aware Analysis for Worst-Case Traversal Time of Real-Time Traffic over RRA-based NoCs
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.ORCID-id: 0000-0001-9736-8490
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.ORCID-id: 0000-0002-1276-3609
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.ORCID-id: 0000-0002-1687-930X
Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.ORCID-id: 0000-0001-6132-7945
2017 (engelsk)Inngår i: Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017, 2017, s. 567-575, artikkel-id 7912705Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Network-on-Chip (NoC) is a communication sub-system which has been widely utilized in many-core processors and system-on-chips in general. In order to execute time-critical applications on a NoC-based platform, the timing behavior of the network needs to be predicted during system design. One of the most important timing requirements is regarding schedulability, which refers to determining if a real-time packet can be delivered within a specific time duration. To verify the fulfillment of such timing requirement, a proper timing analysis is mandatory. Our work focuses on a Round-Robin Arbitration (RRA) based wormhole-switched NoC, which is a common architecture used in many of the existing implementations. Recursive Calculus (RC) is one of the existing analysis approaches for RRA-based NoCs which has been utilized in many research works. However, RC does not take buffer-effects into account. As a result, while performing RC on most of the existing RRA-based NoC designs, it can produce unsafe estimates which is not acceptable for time-critical systems. In this paper, we identify the optimistic problem of RC, and we propose a Revised Recursive Calculus (RRC) which extends RC by considering buffer-effects as well as supporting packetization.

sted, utgiver, år, opplag, sider
2017. s. 567-575, artikkel-id 7912705
Serie
Euromicro Conference on Parallel Distributed and Network-Based Processing, ISSN 1066-6192
Emneord [en]
Many-CoreNetwork-on-ChipBufferTiming Analysis
HSV kategori
Identifikatorer
URN: urn:nbn:se:mdh:diva-34101DOI: 10.1109/PDP.2017.37ISI: 000403395100086Scopus ID: 2-s2.0-85019596935ISBN: 9781509060580 (tryckt)OAI: oai:DiVA.org:mdh-34101DiVA, id: diva2:1056452
Konferanse
25th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing PDP'17, 6-8 Mar 2017, Saint-Petersburg, Russian Federation
Prosjekter
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and ControlTilgjengelig fra: 2016-12-14 Laget: 2016-12-13 Sist oppdatert: 2017-07-06bibliografisk kontrollert
Inngår i avhandling
1. Real-Time Communication over Wormhole-Switched On-Chip Networks
Åpne denne publikasjonen i ny fane eller vindu >>Real-Time Communication over Wormhole-Switched On-Chip Networks
2017 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

In a modern industrial system, the requirement on computational capacity has increased dramatically, in order to support a higher number of functionalities, to process a larger amount of data or to make faster and safer run-time decisions. Instead of using a traditional single-core processor where threads can only be executed sequentially, multi-core and many-core processors are gaining more and more attentions nowadays. In a multi-core processor, software programs can be executed in parallel, which can thus boost the computational performance. Many-core processors are specialized multi-core processors with a larger number of cores which are designed to achieve a higher degree of parallel processing. An on-chip communication bus is a central intersection used for data-exchange between cores, memory and I/O in most multi-core processors. As the number of cores increases, more contention can occur on the communication bus which raises a bottleneck of the overall performance. Therefore, in order to reduce contention incurred on the communication bus, a many-core processor typically employs a Network-on-Chip (NoC) to achieve data-exchange. Real-time embedded systems have been widely utilized for decades. In addition to the correctness of functionalities, timeliness is also an important factor in such systems. Violation of specific timing requirements can result in performance degradation or even fatal problems. While executing real-time applications on many-core processors, the timeliness of a NoC, as a communication subsystem, is essential as well. Unfortunately, many real-time system designs over-provision resources to guarantee the fulfillment of timing requirements, which can lead to significant resource waste. For example, analysis of a NoC design yields that the network is already saturated (i.e. accepting more traffic can incur requirement violation), however, in reality the network actually has the capacity to admit more traffic. In this thesis, we target such resource wasting problems related to design and analysis of NoCs that are used in real-time systems. We propose a number of solutions to improve the schedulability of real-time traffic over wormhole-switched NoCs in order to further improve the resource utilization of the whole system. The solutions focus mainly on two aspects: (1) providing more accurate and efficient time analyses; (2) proposing more cost-effective scheduling methods.

sted, utgiver, år, opplag, sider
Västerås: Malardalen University Press, 2017
Serie
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 232
Emneord
real-time system, network-on-chips
HSV kategori
Forskningsprogram
datavetenskap
Identifikatorer
urn:nbn:se:mdh:diva-35316 (URN)978-91-7485-332-2 (ISBN)
Disputas
2017-06-20, Gamma, Västerås, 09:15 (engelsk)
Opponent
Veileder
Tilgjengelig fra: 2017-05-15 Laget: 2017-05-12 Sist oppdatert: 2017-07-10bibliografisk kontrollert

Open Access i DiVA

Fulltekst mangler i DiVA

Andre lenker

Forlagets fulltekstScopus

Personposter BETA

Liu, MengBecker, MatthiasBehnam, MorisNolte, Thomas

Søk i DiVA

Av forfatter/redaktør
Liu, MengBecker, MatthiasBehnam, MorisNolte, Thomas
Av organisasjonen

Søk utenfor DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric

doi
isbn
urn-nbn
Totalt: 69 treff
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf