Let's study whole-program cache behaviour analytically
2002 (English)In: Proceedings - International Symposium on High-Performance Computer Architecture, 2002, p. 175-186Conference paper, Published paper (Refereed)
Resource type
Text
Abstract [en]
Based on a new characterisation of data reuse across multiple loop nests, we preset a method, a prototyping implementation and some experimental results for analysing the cache behaviour of whole programs with regular computations. Validation against cache simulation using real codes shows the efficiency and accuracy of our method. The largest program, we have analysed, Applu from SPECfP95, has 3868 lines, 16 subroutines and 2565 references. In the case of a 32KB cache with a 32B line size, our method obtains the miss ratio with an absolute error of about 0.80% in about 128 seconds while the simulator used runs for nearly 5 hours on a 933MHz Pentium. III PC. Our method can be used to guide compiler locality optimisations and improve cache simulation performance.
Place, publisher, year, edition, pages
2002. p. 175-186
Keywords [en]
Boolean functions, Computer architecture, Data structures, Computer software reusability, Subroutines, Supercomputers, Absolute error, Cache simulation, Data reuse, Multiple loops, Optimisations, Pentium, Real code
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:mdh:diva-30654DOI: 10.1109/HPCA.2002.995708Scopus ID: 2-s2.0-84949805844ISBN: 0769515258 (print)OAI: oai:DiVA.org:mdh-30654DiVA, id: diva2:890020
Conference
8th International Symposium on High-Performance Computer Architecture, HPCA 2002, 2 February 2002 through 6 February 2002
Note
Export Date: 30 December 2015
2015-12-302015-12-302015-12-30Bibliographically approved