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Probabilistic schedulability guarantees for dependable real-time systems under error bursts
Mälardalen University, School of Innovation, Design and Engineering.ORCID iD: 0000-0001-5053-6725
Mälardalen University, School of Innovation, Design and Engineering.ORCID iD: 0000-0003-4157-3537
SP Technical Research Institute of Sweden.
2011 (English)In: Proc. 10th IEEE Int. Conf. on Trust, Security and Privacy in Computing and Communications, TrustCom 2011, 8th IEEE Int. Conf. on Embedded Software and Systems, ICESS 2011, 6th Int. Conf. on FCST 2011, 2011, p. 1154-1163Conference paper, Published paper (Refereed)
Abstract [en]

The fundamental requirement for the design of effective and efficient fault-tolerance mechanisms in dependable real-time systems is a realistic and applicable model of potential faults, their manifestations and consequences. Fault and error models also need to be evolved based on the characteristics of the operational environments or even based on technological advances. In this paper we propose a probabilistic burst error model in lieu of the commonly used simplistic fault assumptions in the context of processor scheduling. We present a novel schedulability analysis that accounts for the worst case interference caused by error bursts on the response times of tasks scheduled under the fixed priority scheduling (FPS) policy. Further, we describe a methodology for the calculation of probabilistic schedulability guarantees as a weighted sum of the conditional probabilities of schedulability under specified error burst characteristics. Finally, we identify potential sources of pessimism in the worst case response time calculations and discuss potential means for circumventing these issues.

Place, publisher, year, edition, pages
2011. p. 1154-1163
Keywords [en]
dependability, error bursts, fault tolerant scheduling, real-time systems, Burst errors, Conditional probabilities, Error model, Fault tolerance mechanisms, Fixed priority scheduling, Operational environments, Potential faults, Potential sources, Processor scheduling, Schedulability, Schedulability analysis, Technological advances, Weighted Sum, Worst case, Worst case response time, Embedded software, Embedded systems, Fault tolerance, Response time (computer systems), Scheduling, Real time systems
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-15982DOI: 10.1109/TrustCom.2011.157ISI: 000410208500158Scopus ID: 2-s2.0-84856203467ISBN: 9780769546001 (print)OAI: oai:DiVA.org:mdh-15982DiVA, id: diva2:581559
Conference
10th IEEE Int. Conf. on Trust, Security and Privacy in Computing and Communications, TrustCom 2011, 8th IEEE Int. Conf. on Embedded Software and Systems, ICESS 2011, 6th Int. Conf. on Frontier of Computer Science and Technology, FCST 2011, 16 November 2011 through 18 November 2011, Changsha
Note

Sponsors: IEEE TCSC; Central South University; National Natural Science Foundation of China (NSFC); StFX University; Zhejiang University

Available from: 2013-01-02 Created: 2012-10-29 Last updated: 2018-08-10Bibliographically approved

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Aysan, HüseyinDobrin, RaduPunnekkat, Sasikumar

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