mdh.sePublications
Change search
Link to record
Permanent link

Direct link
BETA
Publications (10 of 31) Show all publications
Becker, M., Mubeen, S., Behnam, M. & Nolte, T. (2018). Extending Automotive Legacy Systems with Existing End-to-End Timing Constraints. In: 14th International Conference on Information Technology : New Generations ITNG'17: . Paper presented at 14th International Conference on Information Technology : New Generations ITNG'17, 10-12 Apr 2017, Las Vegas, United States (pp. 597-605). , 558
Open this publication in new window or tab >>Extending Automotive Legacy Systems with Existing End-to-End Timing Constraints
2018 (English)In: 14th International Conference on Information Technology : New Generations ITNG'17, 2018, Vol. 558, p. 597-605Conference paper, Published paper (Refereed)
Abstract [en]

Developing automotive software is becoming in- creasingly challenging due to continuous increase in its size and complexity. The development challenge is amplified when the industrial requirements dictate extensions to the legacy (previously developed) automotive software while requiring to meet the existing timing requirements. To cope with these challenges, sufficient techniques and tooling to support the modeling and timing analysis of such systems at earlier development phases is needed. Within this context, we focus on the extension of software component chains in the software architectures of automotive legacy systems. Selecting the sampling frequency, i.e. period, for newly added software components is crucial to meet the timing requirements of the chains. The challenges in selecting periods are identified. It is further shown how to automatically assign periods to software components, such that the end-to-end timing requirements are met while the runtime overhead is minimized. An industrial case study is presented that demonstrates the applicability of the proposed solution to industrial problems.

Keywords
AutomotiveDesign LevelAbstractionTiming AnalysisEnd-to-EndData AgeRealTime
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-35440 (URN)2-s2.0-85048328854 (Scopus ID)9783319549774 (ISBN)
Conference
14th International Conference on Information Technology : New Generations ITNG'17, 10-12 Apr 2017, Las Vegas, United States
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and ControlPreView: Developing Predictable Vehicle Software on Multi-core
Available from: 2017-06-09 Created: 2017-06-09 Last updated: 2018-06-21Bibliographically approved
Becker, M., Mubeen, S., Dasari, D., Behnam, M. & Nolte, T. (2018). Scheduling Multi-Rate Real-Time Applications on Clustered Many-Core Architectures with Memory Constraints. In: 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC): . Paper presented at 23rd Asia and South Pacific Design Automation Conference ASP-DAC'18, 22 Jan 2018, Jeju Island, South Korea (pp. 560-567).
Open this publication in new window or tab >>Scheduling Multi-Rate Real-Time Applications on Clustered Many-Core Architectures with Memory Constraints
Show others...
2018 (English)In: 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2018, p. 560-567Conference paper, Published paper (Refereed)
Abstract [en]

Access to shared memory is one of the main chal- lenges for many-core processors. One group of scheduling strategies for such platforms focuses on the division of tasks’ access to shared memory and code execution. This allows to orchestrate the access to shared local and off-chip memory in a way such that access contention between different compute cores is avoided by design. In this work, an execution framework is introduced that leverages local memory by statically allocating a subset of tasks to cores. This reduces the access times to shared memory, as off-chip memory access is avoided, and in turn improves the schedulability of such systems. A Constrained Programming (CP) formulation is presented to selects the statically allocated tasks and generates the complete system schedule. Evaluations show that the pro- posed approach yields an up to 21% higher schedulability ratio than related work, and a case study demonstrates its applicability to industrial problems.

Keywords
Many-CoreContention-Free ExecutionReal-TimeMemory Constraints
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-37064 (URN)000426987100108 ()2-s2.0-85045349833 (Scopus ID)978-1-5090-0602-1 (ISBN)
Conference
23rd Asia and South Pacific Design Automation Conference ASP-DAC'18, 22 Jan 2018, Jeju Island, South Korea
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and ControlPreView: Developing Predictable Vehicle Software on Multi-core
Available from: 2017-11-02 Created: 2017-11-02 Last updated: 2018-04-26Bibliographically approved
Becker, M. & Mubeen, S. (2018). Timing Analysis Driven Design-Space Exploration of Cause-Effect Chains in Automotive Systems. In: 44th Annual Conference of the IEEE Industrial Electronics Society IECON'18: . Paper presented at 44th Annual Conference of the IEEE Industrial Electronics Society IECON'18, 21 Oct 2018, Washington DC, United States (pp. 4090-4095). Washington DC, United States, Article ID 8592842.
Open this publication in new window or tab >>Timing Analysis Driven Design-Space Exploration of Cause-Effect Chains in Automotive Systems
2018 (English)In: 44th Annual Conference of the IEEE Industrial Electronics Society IECON'18, Washington DC, United States, 2018, p. 4090-4095, article id 8592842Conference paper, Published paper (Refereed)
Abstract [en]

Model-based development and component-based software engineering have emerged as a promising approach to deal with enormous software complexity in automotive systems. This approach supports the development of software architectures by interconnecting (and reusing) software components (SWCs) at various abstraction levels. Automotive software architectures are often modeled with chains of SWCs, also called cause-effect chains that are constrained by timing requirements. Based on the variations in activation patterns of SWCs, a single model of a cause-effect chain at a higher abstraction level can conform to several valid refined models of the chain at a lower abstraction level, which is closer to the system implementation. As a consequence, the total number of valid implementation-level models generated by the existing techniques increases exponentially, thereby significantly increasing the runtime of the timing analysis engines and liming the scalability of the existing techniques. This paper computes an upper bound on the activation pattern combinations that may result from a system of cause-effect chains in a given high-level model of the software architecture. An efficient algorithm is presented that traverses only a reduced number of possible combinations of the cause-effect chains, resulting in the timing analysis of significantly lower number of implementation-level models of the software architecture. A proof of concept is provided by conducting a case study that shows significant reduction in the runtime of timing analysis engines, i.e., the timing behavior of the considered system is verified by performing the timing analysis of only 27% of all possible combinations of the cause-effect chains.

Place, publisher, year, edition, pages
Washington DC, United States: , 2018
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-40891 (URN)10.1109/IECON.2018.8592842 (DOI)2-s2.0-85061538850 (Scopus ID)9781509066841 (ISBN)
Conference
44th Annual Conference of the IEEE Industrial Electronics Society IECON'18, 21 Oct 2018, Washington DC, United States
Projects
DPAC - Dependable Platforms for Autonomous systems and ControlPreView: Developing Predictable Vehicle Software on Multi-core
Available from: 2018-09-12 Created: 2018-09-12 Last updated: 2019-04-02Bibliographically approved
Becker, M., Mubeen, S., Dasari, D., Behnam, M. & Nolte, T. (2017). A Generic Framework Facilitating Early Analysis of Data Propagation Delays in Multi-Rate Systems. In: The 23th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'17: . Paper presented at The 23th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'17, 16 Aug 2017, Hsinchu, Taiwan. , Article ID 8046323.
Open this publication in new window or tab >>A Generic Framework Facilitating Early Analysis of Data Propagation Delays in Multi-Rate Systems
Show others...
2017 (English)In: The 23th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'17, 2017, article id 8046323Conference paper, Published paper (Refereed)
Abstract [en]

A majority of multi-rate real-time systems are constrained by a multitude of timing requirements, in addition to the traditional deadlines on well-studied response times. This means, the timing predictability of these systems not only depends on the schedulability of certain task sets but also on the timely propagation of data through the chains of tasks from sensors to actuators. In the automotive industry, four different timing constraints corresponding to various data propagation delays are commonly specified on the systems. This paper identifies and addresses the source of pessimism as well as optimism in the calculations for one such delay, namely the reaction delay, in the state-of-the-art analysis that is already implemented in several industrial tools. Furthermore, a generic framework is proposed to compute all the four end-to-end data propagation delays, complying with the established delay semantics, in a scheduler and hardware-agnostic manner. This allows analysis of the system models already at early development phases, where limited system information is present. The paper further introduces mechanisms to generate job-level dependencies, a partial ordering of jobs, which need to be satisfied by any execution platform in order to meet the data propagation timing requirements. The job-level dependencies are first added to all task chains of the system and then reduced to its minimum required set such that the job order is not affected. Moreover, a necessary schedulability test is provided, allowing for varying the number of CPUs. The experimental evaluations demonstrate the tightness in the reaction delay with the proposed framework as compared to the existing state-of-the-art and practice solutions.

Keywords
Data Propagation Delay, End-to-End Delay, Real-Time, Automotive
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-37034 (URN)10.1109/RTCSA.2017.8046323 (DOI)000425851000021 ()2-s2.0-85032739692 (Scopus ID)
Conference
The 23th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'17, 16 Aug 2017, Hsinchu, Taiwan
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and ControlPreView: Developing Predictable Vehicle Software on Multi-core
Available from: 2017-11-02 Created: 2017-11-02 Last updated: 2018-03-15Bibliographically approved
Liu, M., Becker, M., Behnam, M. & Nolte, T. (2017). A Tighter Recursive Calculus to Compute the Worst-Case Traversal Time of Real-Time Traffic over NoCs. In: 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC): . Paper presented at 22nd Asia and South Pacific Design Automation Conference ASP-DAC'17, 16-19 Jan 2017, Chiba / Tokyo, Japan (pp. 275-282). , Article ID 7858332.
Open this publication in new window or tab >>A Tighter Recursive Calculus to Compute the Worst-Case Traversal Time of Real-Time Traffic over NoCs
2017 (English)In: 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2017, p. 275-282, article id 7858332Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) is a communication subsystem which has been widely utilized in many-core processors and system-on-chips in general. In this paper, we focus on a Round-Robin Arbitration (RRA) based wormhole-switched NoC which is a common architecture used in most of the existing implementations. In order to execute real-time applications on such a NoC based platform, a number of given real-time requirements need to be fulfilled. One of the most typical requirements is schedulability which refers to if real-time packets can be delivered within the given time durations. Timing analysis is a common tool to verify the schedulability of a real-time system. Unfortunately, the existing timing analyses of RRA-based NoCs either provide too pessimistic estimates which results in overly allocated resources, or require a large amount of processing which limits the applicability in reality. Therefore, in this paper, we present an improved timing analysis, aiming to provide more accurate estimates along with acceptable computation time. From the evaluation results, we can clearly observe the improvement achieved by the proposed timing analysis.

Series
Asia and South Pacific Design Automation Conference Proceedings, ISSN 2153-6961
Keywords
Network-on-ChipRound-RobinAnalysisWorst-Case Traversal Time
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-33807 (URN)10.1109/ASPDAC.2017.7858332 (DOI)000403609600059 ()2-s2.0-85015318423 (Scopus ID)978-1-5090-1558-0 (ISBN)
Conference
22nd Asia and South Pacific Design Automation Conference ASP-DAC'17, 16-19 Jan 2017, Chiba / Tokyo, Japan
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and Control
Available from: 2016-11-21 Created: 2016-11-21 Last updated: 2017-07-06Bibliographically approved
Becker, M., Dasari, D., Mubeen, S., Behnam, M. & Nolte, T. (2017). Analyzing end-to-end delays in automotive systems at various levels of timing information. Paper presented at 4th International Workshop on Real-time Computing and Distributed Systems in Emergent Applications (REACTION 16). ACM SIGBED Review, 14(4), 8-13
Open this publication in new window or tab >>Analyzing end-to-end delays in automotive systems at various levels of timing information
Show others...
2017 (English)In: ACM SIGBED Review, E-ISSN 1551-3688, Vol. 14, no 4, p. 8-13Article in journal (Refereed) Published
Abstract [en]

Software design for automotive systems is highly complex due to the presence of strict data age constraints for event chains in addition to task specific requirements. These age constraints define the maximum time for the propagation of data through an event chain consisting of independently triggered tasks. Tasks in event chains can have different periods, introducing over- and under-sampling effects, which additionally aggravates their timing analysis. Furthermore, different functionality in these systems, is developed by different suppliers before the final system integration on the ECU. The software itself is developed in a hardware agnostic manner and this uncertainty and limited information at the early design phases may not allow effective analysis of end-to-end delays during that phase. In this paper, we present a method to compute end-to-end delays given the information available in the design phases, thereby enabling timing analysis throughout the development process. The presented methods are evaluated with extensive experiments where the decreasing pessimism with increasing system information is shown.

National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-41839 (URN)10.1145/3177803.3177805 (DOI)
Conference
4th International Workshop on Real-time Computing and Distributed Systems in Emergent Applications (REACTION 16)
Available from: 2018-12-27 Created: 2018-12-27 Last updated: 2018-12-27Bibliographically approved
Liu, M., Becker, M., Behnam, M. & Nolte, T. (2017). Buffer-Aware Analysis for Worst-Case Traversal Time of Real-Time Traffic over RRA-based NoCs. In: Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017: . Paper presented at 25th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing PDP'17, 6-8 Mar 2017, Saint-Petersburg, Russian Federation (pp. 567-575). , Article ID 7912705.
Open this publication in new window or tab >>Buffer-Aware Analysis for Worst-Case Traversal Time of Real-Time Traffic over RRA-based NoCs
2017 (English)In: Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017, 2017, p. 567-575, article id 7912705Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) is a communication sub-system which has been widely utilized in many-core processors and system-on-chips in general. In order to execute time-critical applications on a NoC-based platform, the timing behavior of the network needs to be predicted during system design. One of the most important timing requirements is regarding schedulability, which refers to determining if a real-time packet can be delivered within a specific time duration. To verify the fulfillment of such timing requirement, a proper timing analysis is mandatory. Our work focuses on a Round-Robin Arbitration (RRA) based wormhole-switched NoC, which is a common architecture used in many of the existing implementations. Recursive Calculus (RC) is one of the existing analysis approaches for RRA-based NoCs which has been utilized in many research works. However, RC does not take buffer-effects into account. As a result, while performing RC on most of the existing RRA-based NoC designs, it can produce unsafe estimates which is not acceptable for time-critical systems. In this paper, we identify the optimistic problem of RC, and we propose a Revised Recursive Calculus (RRC) which extends RC by considering buffer-effects as well as supporting packetization.

Series
Euromicro Conference on Parallel Distributed and Network-Based Processing, ISSN 1066-6192
Keywords
Many-CoreNetwork-on-ChipBufferTiming Analysis
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-34101 (URN)10.1109/PDP.2017.37 (DOI)000403395100086 ()2-s2.0-85019596935 (Scopus ID)9781509060580 (ISBN)
Conference
25th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing PDP'17, 6-8 Mar 2017, Saint-Petersburg, Russian Federation
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and Control
Available from: 2016-12-14 Created: 2016-12-13 Last updated: 2017-07-06Bibliographically approved
Becker, M. (2017). Consolidating Automotive Applications on Clustered Many-Core Platforms. In: SIGDA Student Research Forum at ASP-DAC ASP-DAC SRF'17: . Paper presented at SIGDA Student Research Forum at ASP-DAC ASP-DAC SRF'17, 17-19 Jan 2017, Chiba, Japan.
Open this publication in new window or tab >>Consolidating Automotive Applications on Clustered Many-Core Platforms
2017 (English)In: SIGDA Student Research Forum at ASP-DAC ASP-DAC SRF'17, 2017Conference paper, Published paper (Refereed)
Abstract [en]

The increased proliferation of automotive systems is leading to a paradigm shift in the automotive system architecture. Several, now distributed, applications will be consolidated on fewer, more powerful platforms, containing tens or hundreds of compute cores. Clustered many-core processors are a promising candidate for such systems, since each cluster provides enough computational power to host complex applications, while their intrinsic hardware architecture isolates different cluster from each other. The described PhD project works towards methods that allow the consolidation of automotive applications on clustered many-core architectures, while all their timing requirements are maintained. A contention-free execution framework is proposed that successfully diminishes the access-delays due to contention on shared resources within a cluster. In order to integrate complex end-to-end constraints on multi-rate chains, a method is proposed that allows the analysis of such chains and generates job-level dependencies. Such job-level dependencies can then be used to integrate the end-to-end constraints into the proposed execution framework. The applicability of the proposed methods to industrial problems is demonstrated via industrial case studies.

Keywords
Many-CoreConsolidatingAutomotiveReal-TimeNetwork-on-ChipAge-Constraint
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-34104 (URN)
Conference
SIGDA Student Research Forum at ASP-DAC ASP-DAC SRF'17, 17-19 Jan 2017, Chiba, Japan
Projects
PREMISE - Predictable Multicore Systems
Available from: 2016-12-15 Created: 2016-12-13 Last updated: 2017-04-03Bibliographically approved
Becker, M. (2017). Consolidating Automotive Real-Time Applications on Many-Core Platforms. (Doctoral dissertation). Västerås: Malardalen University
Open this publication in new window or tab >>Consolidating Automotive Real-Time Applications on Many-Core Platforms
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Automotive systems have transitioned from basic transportation utilities to sophisticated systems. The rapid increase in functionality comes along with a steep increase in software complexity. This manifests itself in a surge of the number of functionalities as well as the complexity of existing functions. To cope with this transition, current trends shift away from today’s distributed architectures towards integrated architectures, where previously distributed functionality is consolidated on fewer, more powerful, computers. This can ease the integration process, reduce the hardware complexity, and ultimately save costs.

One promising hardware platform for these powerful embedded computers is the many-core processor. A many-core processor hosts a vast number of compute cores, that are partitioned on tiles which are connected by a Network-on-Chip. These natural partitions can provide exclusive execution spaces for different applications, since most resources are not shared among them. Hence, natural building blocks towards temporally and spatially separated execution spaces exist as a result of the hardware architecture.

Additionally to the traditional task local deadlines, automotive applications are often subject to timing constraints on the data propagation through a chain of semantically related tasks. Such requirements pose challenges to the system designer as they are only able to verify them after the system synthesis (i.e. very late in the design process).

In this thesis, we present methods that transform complex timing constraints on the data propagation delay to precedence constraints between individual jobs. An execution framework for the cluster of the many-core is proposed that allows access to cluster external memory while it avoids contention on shared resources by design. A partitioning and configuration of the Network-on-Chip provides isolation between the different applications and reduces the access time from the clusters to external memory. Moreover, methods that facilitate the verification of data propagation delays in each development step are provided. 

Place, publisher, year, edition, pages
Västerås: Malardalen University, 2017
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 246
Keywords
Many-Core, Automotive, Network-on-Chip, Real-Time, Timing analysis
National Category
Embedded Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-37182 (URN)978-91-7485-359-9 (ISBN)
Public defence
2017-12-19, Kappa, Mälardalens högskola, Västerås, 09:00 (English)
Opponent
Supervisors
Available from: 2017-11-06 Created: 2017-11-02 Last updated: 2017-11-27Bibliographically approved
Becker, M., Dasari, D., Mubeen, S., Behnam, M. & Nolte, T. (2017). End-to-End Timing Analysis of Cause-Effect Chains in Automotive Embedded Systems. Journal of systems architecture, 80(Supplement C), 104-113
Open this publication in new window or tab >>End-to-End Timing Analysis of Cause-Effect Chains in Automotive Embedded Systems
Show others...
2017 (English)In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 80, no Supplement C, p. 104-113Article in journal (Refereed) Published
Abstract [en]

Automotive embedded systems are subjected to stringent timing requirements that need to be verified. One of the most complex timing requirement in these systems is the data age constraint. This constraint is specified on cause- effect chains and restricts the maximum time for the propagation of data through the chain. Tasks in a cause-effect chain can have different activation patterns and different periods, that introduce over- and under-sampling effects, which additionally aggravate the end-to-end timing analysis of the chain. Furthermore, the level of timing information available at various development stages (from modeling of the software architecture to the software implementation) varies a lot, the complete timing information is available only at the implementation stage. This uncertainty and limited timing information can restrict the end-to-end timing analysis of these chains. In this paper, we present methods to compute end-to-end delays based on different levels of system information. The characteristics of different communication semantics are further taken into account, thereby enabling timing analysis throughout the development process of such heterogeneous software systems. The presented methods are evaluated with extensive experiments. As a proof of concept, an industrial case study demonstrates the applicability of the proposed methods following a state-of-the-practice development process.

Keywords
Data Propagation DelayAutomotive Real-Time
National Category
Embedded Systems
Identifiers
urn:nbn:se:mdh:diva-37084 (URN)10.1016/j.sysarc.2017.09.004 (DOI)000413883100010 ()2-s2.0-85031742078 (Scopus ID)
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and ControlPreView: Developing Predictable Vehicle Software on Multi-core
Available from: 2017-10-27 Created: 2017-10-27 Last updated: 2017-11-16Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-1276-3609

Search in DiVA

Show all publications