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Publications (10 of 24) Show all publications
Vitucci, C., Sundmark, D., Danielsson, J., Marcus, J., Larsson, A. & Nolte, T. (2023). Run Time Memory Error Recovery Process in Networking System. In: Int. Conf. Syst. Reliab. Saf., ICSRS: . Paper presented at 2023 7th International Conference on System Reliability and Safety, ICSRS 2023 (pp. 590-597). Institute of Electrical and Electronics Engineers Inc.
Open this publication in new window or tab >>Run Time Memory Error Recovery Process in Networking System
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2023 (English)In: Int. Conf. Syst. Reliab. Saf., ICSRS, Institute of Electrical and Electronics Engineers Inc. , 2023, p. 590-597Conference paper, Published paper (Refereed)
Abstract [en]

System memory errors have always been problematic; today, they cause more than forty percent of confirmed hardware errors in repair centers for both data centers and telecommunications network nodes. Therefore, it is somewhat expected that, in recent years, device manufacturers improved the hardware features to support hardware-assisted fault management implementation. For example, the new standard, DDR5, includes both data redundancy, the so-called Error Correcting Code (ECC), and physical redundancy, the post-package repair (PPR), as mandatory features. Production and repair centers mainly use physical redundancy to replace faulty memory rows. In contrast, field use still needs to be improved, mainly due to a need for integrated system solutions for network nodes. This paper aims to compensate for this shortcoming and presents a system solution for handling memory errors. It is a multi-technology proposition (mixed use of ECC and PPR) based on multi-layer (hardware, firmware, and software) error information exchange.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2023
Keywords
Error Correcting Code, Fault Management, Memory Faults, Post-Package Repair, Run Time Fault Recovering, Error correction, Failure analysis, Firmware, Repair, Hardware error, Memory error, Network node, Runtimes, System solution, Redundancy
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:mdh:diva-65954 (URN)10.1109/ICSRS59833.2023.10381346 (DOI)2-s2.0-85183463653 (Scopus ID)9798350306057 (ISBN)
Conference
2023 7th International Conference on System Reliability and Safety, ICSRS 2023
Available from: 2024-02-07 Created: 2024-02-07 Last updated: 2024-02-07Bibliographically approved
Imtiaz, S., Behnam, M., Capannini, G., Carlson, J. & Marcus, J. (2022). Automatic Segmentation of Resource Utilization Data. In: 1st IEEE Industrial Electronics Society Annual On-Line Conference (ONCON) 2022: . Paper presented at 2022 IEEE 1st Industrial Electronics Society Annual On-Line Conference (ONCON), 09-11 December 2022, Kharagpur, India.
Open this publication in new window or tab >>Automatic Segmentation of Resource Utilization Data
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2022 (English)In: 1st IEEE Industrial Electronics Society Annual On-Line Conference (ONCON) 2022, 2022Conference paper, Published paper (Other academic)
Abstract [en]

Advancement of industrial systems seek improvements to achieve required level of quality of service and efficient performance management. It is essential though to have better understanding of resource utilization behaviour of applications in execution. Even the expert engineers desire to envision dependencies and impact of one computer resource on the other. For such situations it is significant to know statistical relationship between data sets such as a resource with higher cache demand should not be scheduled together with other cache hungry process at the same time and same core. Performance monitoring data coming from hardware and software is huge and grouping of this time series data based on similar behaviour can display distinguishable execution phases. For benefits like these we opt to choose change point analysis method. By using this method study determined the optimal threshold which can identify more or less same segments for other executions of same application and same event. These segments are then validated with the help of test data. Finally the study provided segment-wise, local, compact statistical model with decent accuracy.

National Category
Computer Sciences
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-61461 (URN)10.1109/ONCON56984.2022.10126744 (DOI)2-s2.0-85161320276 (Scopus ID)979-8-3503-9806-9 (ISBN)
Conference
2022 IEEE 1st Industrial Electronics Society Annual On-Line Conference (ONCON), 09-11 December 2022, Kharagpur, India
Available from: 2023-01-11 Created: 2023-01-11 Last updated: 2023-09-19Bibliographically approved
Danielsson, J., Seceleanu, T., Marcus, J., Behnam, M. & Sjödin, M. (2021). Automatic Quality of Service Control in Multi-core Systems using Cache Partitioning. In: : . Paper presented at Emerging Technologies and Factory Automation (ETFA), 2021. Västerås: Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Automatic Quality of Service Control in Multi-core Systems using Cache Partitioning
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2021 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we present a last-level cache partitioning controller for multi-core systems. Our objective is to control the Quality of Service (QoS) of applications in multi-core systems by monitoring run-time performance and continuously re-sizing cache partition sizes according to the applications' needs. We discuss two different use-cases; one that promotes application fairness and another one that prioritizes applications according to the system engineers' desired execution behavior. We display the performance drawbacks of maintaining a fair schedule for all system tasks and its performance implications for system applications. We, therefore, implement a second control algorithm that enforces cache partition assignments according to user-defined priorities rather than system fairness. Our experiments reveal that it is possible, with non-instrusive (0.3-0.7\% CPU utilization) cache controlling measures, to increase performance according to setpoints and maintain the QoS for specific applications in an over-saturated system.

Place, publisher, year, edition, pages
Västerås: Institute of Electrical and Electronics Engineers (IEEE), 2021
National Category
Computer Sciences
Identifiers
urn:nbn:se:mdh:diva-56070 (URN)10.1109/ETFA45728.2021.9613641 (DOI)000766992600219 ()2-s2.0-85122957047 (Scopus ID)9781728129891 (ISBN)
Conference
Emerging Technologies and Factory Automation (ETFA), 2021
Available from: 2021-10-01 Created: 2021-10-01 Last updated: 2022-06-07Bibliographically approved
Danielsson, J., Seceleanu, T., Marcus, J., Behnam, M. & Sjödin, M. (2021). LLM-shark -- A Tool for Automatic Resource-boundness Analysis and Cache Partitioning Setup. In: 45th IEEE Annual Computers, Software, and Applications Conference, COMPSAC 2021: . Paper presented at COMPSAC 2021 (pp. 49-58).
Open this publication in new window or tab >>LLM-shark -- A Tool for Automatic Resource-boundness Analysis and Cache Partitioning Setup
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2021 (English)In: 45th IEEE Annual Computers, Software, and Applications Conference, COMPSAC 2021, 2021, p. 49-58Conference paper, Published paper (Refereed)
Abstract [en]

We present LLM-shark, a tool for automatic hardware resource-boundness detection and cache-partitioning. Our tool has three primary objectives: First, it determines the hardware resource-boundness of a given application. Secondly, it estimates the initial cache partition size to ensure that the application performance is conserved and not affected by other processes competing for cache utilization. Thirdly, it continuously monitors that the application performance is maintained over time and, if necessary, change the cache partition size. We demonstrate LLM-shark's functionality through a series of tests using six different applications, including a set of feature detection algorithms and two synthetic applications. Our tests reveal that it is possible to determine an application's resource-boundness using a Pearson-correlation scheme implemented in LLM-shark. We propose a scheme to size cache partitions based on the correlation coefficient applications depending on their resource boundness.

National Category
Computer Sciences
Identifiers
urn:nbn:se:mdh:diva-56074 (URN)10.1109/COMPSAC51774.2021.00019 (DOI)000706529000008 ()2-s2.0-85115835802 (Scopus ID)978-1-6654-2463-9 (ISBN)
Conference
COMPSAC 2021
Available from: 2021-10-01 Created: 2021-10-01 Last updated: 2021-11-11Bibliographically approved
Danielsson, J., Janne, S., Marcus, J., Seceleanu, T., Behnam, M. & Sjödin, M. (2021). Modelling Application Cache Behavior using Regression Models. In: IEEE (Ed.), : . Paper presented at The 11th IEEE International Workshop on Industrial Experience in Embedded Systems Design (IEESD 2021). Västerås
Open this publication in new window or tab >>Modelling Application Cache Behavior using Regression Models
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2021 (English)In: / [ed] IEEE, Västerås, 2021Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we describe the creation of resource usage forecasts for applications with unknown execution characteristics, by evaluating different regression processes, including autoregressive, multivariate adaptive regression splines, exponential smoothing, etc. We utilize Performance Monitor Units (PMU) and generate hardware resource usage models for the L-2-cache and the L-3-cache using nine different regression processes. The measurement strategy and regression process methodology are general and applicable to any given hardware resource when performance counters are available. We use three benchmark applications: the SIFT feature detection algorithm, a standard matrix multiplication, and a version of Bubblesort. Our evaluation shows that Multi Adaptive Regressive Spline (MARS) models generate the best resource usage forecasts among the considered models, followed by Single Exponential Splines (SES) and Triple Exponential Splines (TES).

Place, publisher, year, edition, pages
Västerås: , 2021
National Category
Computer Sciences
Identifiers
urn:nbn:se:mdh:diva-56073 (URN)10.1109/COMPSAC51774.2021.00284 (DOI)000706529000273 ()2-s2.0-85115859046 (Scopus ID)978-1-6654-2463-9 (ISBN)
Conference
The 11th IEEE International Workshop on Industrial Experience in Embedded Systems Design (IEESD 2021)
Available from: 2021-10-01 Created: 2021-10-01 Last updated: 2021-11-11Bibliographically approved
Imtiaz, S., Danielsson, J., Behnam, M., Capannini, G., Carlson, J. & Marcus, J. (2021). Towards Automatic Application Fingerprinting Using Performance Monitoring Counters. In: ACM International Conference Proceeding Series: . Paper presented at 7th Conference on the Engineering of Computer Based Systems, ECBS 2021, 26 May 2021 through 27 May 2021. Association for Computing Machinery
Open this publication in new window or tab >>Towards Automatic Application Fingerprinting Using Performance Monitoring Counters
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2021 (English)In: ACM International Conference Proceeding Series, Association for Computing Machinery , 2021Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we discuss a method for application fingerprinting using conventional hardware and software performance counters. Modern applications are complex and often utilizes a broad spectra of the available hardware resources, where multiple performance counters can be of significant interest. The number of performance counters that can be captured simultaneously is, however, small due to hardware limitations in most modern computers. We propose to mitigate the hardware limitations using an intelligent mechanism that pinpoints the most relevant performance counters for an application's performance. In our proposal, we utilize the Pearson correlation coefficient to rank the most relevant PMU events and filter out events of less relevance to an application's execution. Our ultimate goal is to establish a comparable application fingerprint model using performance counters, that we can use to classify applications. The classification procedure can then be used to determine the type of application's fingerprint, such as malicious software.

Place, publisher, year, edition, pages
Association for Computing Machinery, 2021
Keywords
Computer hardware, Correlation methods, Application fingerprinting, Automatic application, Classification procedure, Hardware and software, Intelligent mechanisms, Pearson correlation coefficients, Performance counters, Performance monitoring, Application programs
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:mdh:diva-58797 (URN)10.1145/3459960.3461557 (DOI)2-s2.0-85107211777 (Scopus ID)9781450390576 (ISBN)
Conference
7th Conference on the Engineering of Computer Based Systems, ECBS 2021, 26 May 2021 through 27 May 2021
Note

Conference code: 169185; Export Date: 8 June 2022; Conference Paper

Available from: 2022-07-13 Created: 2022-07-13 Last updated: 2022-11-08Bibliographically approved
Danielsson, J., Seceleanu, T., Marcus, J., Behnam, M. & Nolin, M. (2020). Resource Depedency Analysis in Multi-Core Systems. In: Proceedings - 2020 IEEE 44th Annual Computers, Software, and Applications Conference, COMPSAC 2020: . Paper presented at 44th IEEE Annual Computers, Software, and Applications Conference, COMPSAC 2020, Virtual, Madrid; Spain; 13 July 2020 through 17 July 2020 (pp. 87-94). Institute of Electrical and Electronics Engineers Inc., Article ID 9202484.
Open this publication in new window or tab >>Resource Depedency Analysis in Multi-Core Systems
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2020 (English)In: Proceedings - 2020 IEEE 44th Annual Computers, Software, and Applications Conference, COMPSAC 2020, Institute of Electrical and Electronics Engineers Inc. , 2020, p. 87-94, article id 9202484Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we evaluate different methods for statistical determination of application resource dependency in multi-core systems. We measure the performance counters of an application during run-time and create a system resource usage profile. We then use the resource profile to evaluate the application dependency on the specific resource. We discuss and evaluate two methods to process the data, including moving average filter and partitioning the data into smaller segments in order to interpret data for correlation calculations. Our aim with this study is to evaluate and create a generalizeable methods for automatic determination of resource dependencies. The final outcome of the methods used in this study is the answer to the question: 'To what resources is this application dependent on?'. The recommendation of this tool will be used in conjunction with our last-level cache partitioning controller (LLC-PC), to make decision if an application should receive last-level cache partition slices.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2020
Keywords
Multi core, Performance counters, Resource boundess, Critical path analysis, Automatic determination, Last-level caches, Moving average filter, Multi-core systems, Resource dependencies, Resource profile, System resources, Application programs
National Category
Embedded Systems
Identifiers
urn:nbn:se:mdh:diva-52391 (URN)10.1109/COMPSAC48688.2020.00021 (DOI)000629086600013 ()2-s2.0-85094161162 (Scopus ID)9781728173030 (ISBN)
Conference
44th IEEE Annual Computers, Software, and Applications Conference, COMPSAC 2020, Virtual, Madrid; Spain; 13 July 2020 through 17 July 2020
Projects
DPACXPRES
Available from: 2020-11-10 Created: 2020-11-10 Last updated: 2022-11-08Bibliographically approved
Danielsson, J., Marcus, J., Seceleanu, T., Behnam, M. & Sjödin, M. (2019). Run-time Cache-Partition Controller for Multi-core Systems. In: : . Paper presented at In 45th Annual Conference of the IEEE Industrial Electronics Society (IECON), 2019.
Open this publication in new window or tab >>Run-time Cache-Partition Controller for Multi-core Systems
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2019 (English)Conference paper, Published paper (Refereed)
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-45949 (URN)10.1109/IECON.2019.8926758 (DOI)000522050604082 ()2-s2.0-85084114345 (Scopus ID)
Conference
In 45th Annual Conference of the IEEE Industrial Electronics Society (IECON), 2019
Available from: 2019-11-11 Created: 2019-11-11 Last updated: 2022-11-08Bibliographically approved
Danielsson, J., Seceleanu, T., Marcus, J., Behnam, M. & Sjödin, M. (2019). Testing Performance-Isolation in Multi-Core Systems. In: : . Paper presented at 43rd IEEE Annual Computer Software and Applications Conference, COMPSAC 2019; Milwaukee; United States; 15 July 2019 through 19 July 2019 (pp. 604-609). , Article ID 8754208.
Open this publication in new window or tab >>Testing Performance-Isolation in Multi-Core Systems
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2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present a methodology to be used for quantifying the level of performance isolation for a multi-core system. We have devised a test that can be applied to breaches of isolation in different computing resources that may be shared between different cores. We use this test to determine the level of isolation gained by using the Jailhouse hypervisor compared to a regular Linux system in terms of CPU isolation, cache isolation and memory bus isolation. Our measurements show that the Jailhouse hypervisor provides performance isolation of local computing resources such as CPU. We have also evaluated if any isolation could be gained for shared computing resources such as the system wide cache and the memory bus controller. Our tests show no measurable difference in partitioning between a regular Linux system and a Jailhouse partitioned system for shared resources. Using the Jailhouse hypervisor provides only a small noticeable overhead when executing multiple shared-resource intensive tasks on multiple cores, which implies that running Jailhouse in a memory saturated system will not be harmful. However, contention still exist in the memory bus and in the system-wide cache.

National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-45947 (URN)10.1109/COMPSAC.2019.00092 (DOI)000538791700081 ()2-s2.0-85072706762 (Scopus ID)978-1-7281-2607-4 (ISBN)
Conference
43rd IEEE Annual Computer Software and Applications Conference, COMPSAC 2019; Milwaukee; United States; 15 July 2019 through 19 July 2019
Available from: 2019-11-11 Created: 2019-11-11 Last updated: 2022-11-08Bibliographically approved
Marcus, J., Ermedahl, A., Eldh, S., Behnam, M. & Lisper, B. (2018). Enforcing Quality of Service Through Hardware Resource Aware Process Scheduling. In: 2018 IEEE 23RD INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION (ETFA): . Paper presented at 23rd IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), SEP 04-07, 2018, Politecnico Torino, Torino, ITALY (pp. 329-336). IEEE
Open this publication in new window or tab >>Enforcing Quality of Service Through Hardware Resource Aware Process Scheduling
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2018 (English)In: 2018 IEEE 23RD INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION (ETFA), IEEE , 2018, p. 329-336Conference paper, Published paper (Refereed)
Abstract [en]

Hardware manufacturers are forced to improve system performance continuously due to advanced and computationally demanding system functions. Unfortunately - more powerful hardware leads to increased costs. Instead, companies attempt to improve performance by consolidating multiple functions to share the same hardware to exploit existing performance instead. In legacy systems, each function had individual execution environment that guaranteed HW resource isolation and therefore the Quality of Service (QoS). Consolidation of multiple functions increases the risk of shared resource congestion. Current process schedulers focus on time quanta and do not consider shared resources. We present a novel process scheduler that complements current process schedulers by enforcing QoS though Shared Resource Aware (SRA) process scheduling. The SRA scheduler programs the Performance Monitoring Unit (PMU) to generate an overflow interrupt when reaching the assigned process resource quota. The scheduler has the possibility to swap out the process when receiving the interrupt allowing it to enforce the QoS for the scheduled process. We have implemented our scheduling policy as a new scheduling class in Linux. Our experiments show that it efficiently enforces QoS without seriously affect the shared resource usage of other processes executing on the same HW.

Place, publisher, year, edition, pages
IEEE, 2018
Series
IEEE International Conference on Emerging Technologies and Factory Automation-ETFA, ISSN 1946-0740
National Category
Computer Engineering Computer Systems
Identifiers
urn:nbn:se:mdh:diva-41379 (URN)10.1109/ETFA.2018.8502609 (DOI)000449334500040 ()2-s2.0-85057231617 (Scopus ID)978-1-5386-7108-5 (ISBN)
Conference
23rd IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), SEP 04-07, 2018, Politecnico Torino, Torino, ITALY
Available from: 2019-10-18 Created: 2019-10-18 Last updated: 2020-10-22Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0003-2612-4135

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