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Ciccozzi, F., Addazi, L., Abbaspour Asadollah, S., Lisper, B., Masud, A. N. & Mubeen, S. (2023). A Comprehensive Exploration of Languages for Parallel Computing. ACM Computing Surveys, 55(2), Article ID 21.
Open this publication in new window or tab >>A Comprehensive Exploration of Languages for Parallel Computing
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2023 (English)In: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341, Vol. 55, no 2, article id 21Article in journal (Refereed) Published
Abstract [en]

Software-intensive systems in most domains, from autonomous vehicles to health, are becoming predominantly parallel to efficiently manage large amount of data in short (even real-) time. There is an incredibly rich literature on languages for parallel computing, thus it is difficult for researchers and practitioners, even experienced in this very field, to get a grasp on them. With this work we provide a comprehensive, structured, and detailed snapshot of documented research on those languages to identify trends, technical characteristics, open challenges, and research directions. In this article, we report on planning, execution, and results of our systematic peer-reviewed as well as grey literature review, which aimed at providing such a snapshot by analysing 225 studies.

Place, publisher, year, edition, pages
ASSOC COMPUTING MACHINERY, 2023
Keywords
Parallel computing, programming, modelling, languages, frameworks, systematic literature review
National Category
Computer Sciences
Identifiers
urn:nbn:se:mdh:diva-58152 (URN)10.1145/3485008 (DOI)000778458900001 ()2-s2.0-85128233360 (Scopus ID)
Available from: 2022-06-23 Created: 2022-06-23 Last updated: 2022-08-29Bibliographically approved
Taheri, M., Riazati, M., Ahmadilivani, M. H., Jenihhin, M., Daneshtalab, M., Raik, J., . . . Lisper, B. (2023). DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. In: Proceedings - International Symposium on Quality Electronic Design, ISQED: . Paper presented at 24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, 5 April 2023 through 7 April 2023. IEEE Computer Society
Open this publication in new window or tab >>DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators
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2023 (English)In: Proceedings - International Symposium on Quality Electronic Design, ISQED, IEEE Computer Society , 2023Conference paper, Published paper (Refereed)
Abstract [en]

While the role of Deep Neural Networks (DNNs) in a wide range of safety-critical applications is expanding, emerging DNNs experience massive growth in terms of computation power. It raises the necessity of improving the reliability of DNN accelerators yet reducing the computational burden on the hardware platforms, i.e. reducing the energy consumption and execution time as well as increasing the efficiency of DNN accelerators. Therefore, the trade-off between hardware performance, i.e. area, power and delay, and the reliability of the DNN accelerator implementation becomes critical and requires tools for analysis.In this paper, we propose a framework DeepAxe for design space exploration for FPGA-based implementation of DNNs by considering the trilateral impact of applying functional approximation on accuracy, reliability and hardware performance. The framework enables selective approximation of reliability-critical DNNs, providing a set of Pareto-optimal DNN implementation design space points for the target resource utilization requirements. The design flow starts with a pre-trained network in Keras, uses an innovative high-level synthesis environment DeepHLS and results in a set of Pareto-optimal design space points as a guide for the designer. The framework is demonstrated on a case study of custom and state-of-the-art DNNs and datasets. 

Place, publisher, year, edition, pages
IEEE Computer Society, 2023
Keywords
approximate computing, deep neural networks, fault simulation, reliability, resiliency assessment
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-63499 (URN)10.1109/ISQED57927.2023.10129353 (DOI)001013619400058 ()2-s2.0-85161606608 (Scopus ID)9798350334753 (ISBN)
Conference
24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, 5 April 2023 through 7 April 2023
Available from: 2023-06-21 Created: 2023-06-21 Last updated: 2023-10-09Bibliographically approved
Lisper, B. & Källberg, L. (2023). HERO-ML: A Very High-Level Array Language for Executable Modelling of Data Parallel Algorithms. In: ARRAY - Proc. ACM SIGPLAN Int. Workshop Libr., Lang. Compil. Array Program., Co-located PLDI: . Paper presented at ARRAY 2023 - Proceedings of the 9th ACM SIGPLAN International Workshop on Libraries, Languages and Compilers for Array Programming, Co-located with PLDI 2023 (pp. 13-21). Association for Computing Machinery, Inc
Open this publication in new window or tab >>HERO-ML: A Very High-Level Array Language for Executable Modelling of Data Parallel Algorithms
2023 (English)In: ARRAY - Proc. ACM SIGPLAN Int. Workshop Libr., Lang. Compil. Array Program., Co-located PLDI, Association for Computing Machinery, Inc , 2023, p. 13-21Conference paper, Published paper (Refereed)
Abstract [en]

HERO-ML is an array language, on very high level, which is intended for specifying data parallel algorithms in a concise and platform-independent way where all the inherent data parallelism is easy to identify. The goal is to support the software development for heterogeneous systems with different kinds of parallel numerical accelerators, where programs tend to be very platform-specific and difficult to develop. In this paper we describe HERO-ML, and a proof-of-concept implementation.

Place, publisher, year, edition, pages
Association for Computing Machinery, Inc, 2023
Keywords
array language, data parallelism, High level languages, Modeling languages, Parallel algorithms, Array languages, Data-parallel algorithms, Executable modeling, Heterogeneous systems, Platform independent, Proof of concept, Software design
National Category
Software Engineering
Identifiers
urn:nbn:se:mdh:diva-65184 (URN)10.1145/3589246.3595370 (DOI)001119200500002 ()2-s2.0-85162636297 (Scopus ID)9798400701696 (ISBN)
Conference
ARRAY 2023 - Proceedings of the 9th ACM SIGPLAN International Workshop on Libraries, Languages and Compilers for Array Programming, Co-located with PLDI 2023
Available from: 2023-12-21 Created: 2023-12-21 Last updated: 2024-01-10Bibliographically approved
Helali Moghadam, M., Borg, M., Saadatmand, M., Mousavirad, S. J., Bohlin, M. & Lisper, B. (2023). Machine learning testing in an ADAS case study using simulation-integrated bio-inspired search-based testing. Journal of Software: Evolution and Process
Open this publication in new window or tab >>Machine learning testing in an ADAS case study using simulation-integrated bio-inspired search-based testing
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2023 (English)In: Journal of Software: Evolution and Process, ISSN 2047-7473, E-ISSN 2047-7481Article in journal (Refereed) Published
Abstract [en]

This paper presents an extended version of Deeper, a search-based simulation-integrated test solution that generates failure-revealing test scenarios for testing a deep neural network-based lane-keeping system. In the newly proposed version, we utilize a new set of bio-inspired search algorithms, genetic algorithm (GA), (Formula presented.) and (Formula presented.) evolution strategies (ES), and particle swarm optimization (PSO), that leverage a quality population seed and domain-specific crossover and mutation operations tailored for the presentation model used for modeling the test scenarios. In order to demonstrate the capabilities of the new test generators within Deeper, we carry out an empirical evaluation and comparison with regard to the results of five participating tools in the cyber-physical systems testing competition at SBST 2021. Our evaluation shows the newly proposed test generators in Deeper not only represent a considerable improvement on the previous version but also prove to be effective and efficient in provoking a considerable number of diverse failure-revealing test scenarios for testing an ML-driven lane-keeping system. They can trigger several failures while promoting test scenario diversity, under a limited test time budget, high target failure severity, and strict speed limit constraints.

Place, publisher, year, edition, pages
John Wiley and Sons Ltd, 2023
Keywords
advanced driver assistance systems, deep learning, evolutionary computation, lane-keeping system, machine learning testing, search-based testing, Automobile drivers, Biomimetics, Budget control, Deep neural networks, Embedded systems, Genetic algorithms, Learning systems, Particle swarm optimization (PSO), Software testing, Case-studies, Lane keeping, Machine-learning, Software Evolution, Software process, Test scenario
National Category
Computer Sciences
Identifiers
urn:nbn:se:mdh:diva-63851 (URN)10.1002/smr.2591 (DOI)001021376500001 ()2-s2.0-85163167144 (Scopus ID)
Available from: 2023-07-12 Created: 2023-07-12 Last updated: 2023-07-19Bibliographically approved
Helali Moghadam, M., Saadatmand, M., Borg, M., Bohlin, M. & Lisper, B. (2022). An Autonomous Performance Testing Framework using Self-Adaptive Fuzzy Reinforcement Learning. Software quality journal, 127-159
Open this publication in new window or tab >>An Autonomous Performance Testing Framework using Self-Adaptive Fuzzy Reinforcement Learning
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2022 (English)In: Software quality journal, ISSN 0963-9314, E-ISSN 1573-1367, p. 127-159Article in journal (Refereed) Published
Abstract [en]

Test automation brings the potential to reduce costs and human effort, but several aspects of software testing remain challenging to automate. One such example is automated performance testing to find performance breaking points. Current approaches to tackle automated generation of performance test cases mainly involve using source code or system model analysis or use-case based techniques. However, source code and system models might not always be available at testing time. On the other hand, if the optimal performance testing policy for the intended objective in a testing process instead could be learnt by the testing system, then test automation without advanced performance models could be possible. Furthermore, the learnt policy could later be reused for similar software systems under test, thus leading to higher test efficiency. We propose SaFReL, a self-adaptive fuzzy reinforcement learning-based performance testing framework. SaFReL learns the optimal policy to generate performance test cases through an initial learning phase, then reuses it during a transfer learning phase, while keeping the learning running and updating the policy in the long term. Through multiple experiments on a simulated environment, we demonstrate that our approach generates the target performance test cases for different programs more efficiently than a typical testing process, and performs adaptively without access to source code and performance models.

Place, publisher, year, edition, pages
Springer, 2022
Keywords
Performance testing, Stress testing, Test case generation, Reinforcement learning, Autonomous testing
National Category
Computer Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-47471 (URN)10.1007/s11219-020-09532-z (DOI)000627215600001 ()2-s2.0-85102446552 (Scopus ID)
Available from: 2020-04-06 Created: 2020-04-06 Last updated: 2023-09-13Bibliographically approved
Malm, J., Enoiu, E. P., Masud, A. N., Lisper, B., Porkoláb, Z. & Eldh, S. (2022). An Evaluation of General-Purpose Static Analysis Tools on C/C++ Test Code. In: Proc. - Euromicro Conf. Softw. Eng. Adv. Appl., SEAA: . Paper presented at Proceedings - 48th Euromicro Conference on Software Engineering and Advanced Applications, SEAA 2022, Gran Canaria, 31 August - 2 September 2022 (pp. 133-140). Institute of Electrical and Electronics Engineers Inc.
Open this publication in new window or tab >>An Evaluation of General-Purpose Static Analysis Tools on C/C++ Test Code
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2022 (English)In: Proc. - Euromicro Conf. Softw. Eng. Adv. Appl., SEAA, Institute of Electrical and Electronics Engineers Inc. , 2022, p. 133-140Conference paper, Published paper (Refereed)
Abstract [en]

In recent years, maintaining test code quality has gained more attention due to increased automation and the growing focus on issues caused during this process. Test code may become long and complex, but maintaining its quality is mostly a manual process, that may not scale in big software projects. Moreover, bugs in test code may give a false impression about the correctness or performance of the production code. Static program analysis (SPA) tools are being used to maintain the quality of software projects nowadays. However, these tools are either not used to analyse test code, or any analysis results on the test code are suppressed. This is especially true since SPA tools are not tailored to generate precise warnings on test code. This paper investigates the use of SPA on test code by employing three state-of-the-art general-purpose static analysers on a curated set of projects used in the industry and a random sample of relatively popular and large open-source C/C++ projects. We have found a number of built-in code checking modules that can detect quality issues in the test code. However, these checkers need some tailoring to obtain relevant results. We observed design choices in test frameworks that raise noisy warnings in analysers and propose a set of augmentations to the checkers or the analysis framework to obtain precise warnings from static analysers.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2022
Keywords
C++ (programming language), Open source software, Open systems, Program debugging, Quality control, Software testing, Static analysis, Analysis tools, Code quality, Faults detection, Manual process, Performance, Quality of softwares, Software project, Static program analysis, Test code, Test maintenances, Fault detection, test maintenance, testing
National Category
Software Engineering
Identifiers
urn:nbn:se:mdh:diva-61960 (URN)10.1109/SEAA56994.2022.00029 (DOI)2-s2.0-85147711435 (Scopus ID)9781665461528 (ISBN)
Conference
Proceedings - 48th Euromicro Conference on Software Engineering and Advanced Applications, SEAA 2022, Gran Canaria, 31 August - 2 September 2022
Available from: 2023-02-22 Created: 2023-02-22 Last updated: 2023-02-23Bibliographically approved
Riazati, M., Daneshtalab, M., Sjödin, M. & Lisper, B. (2022). AutoDeepHLS: Deep Neural Network High-level Synthesis using fixed-point precision. In: 2022 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2022): INTELLIGENT TECHNOLOGY IN THE POST-PANDEMIC ERA. Paper presented at IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) - Intelligent Technology in the Post-Pandemic Era, JUN 13-15, 2022, Incheon, SOUTH KOREA (pp. 122-125). IEEE
Open this publication in new window or tab >>AutoDeepHLS: Deep Neural Network High-level Synthesis using fixed-point precision
2022 (English)In: 2022 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2022): INTELLIGENT TECHNOLOGY IN THE POST-PANDEMIC ERA, IEEE , 2022, p. 122-125Conference paper, Published paper (Refereed)
Abstract [en]

Deep Neural Networks (DNN) have received much attention in various applications such as visual recognition, self-driving cars, health care, etc. Hardware implementation, specifically using FPGA and ASIC due to their high performance and low power consumption, is considered an efficient method. However, implementation on these platforms is difficult for neural network designers since they usually have limited knowledge of hardware. High-Level Synthesis (HLS) tools can act as a bridge between high-level DNN designs and hardware implementation. Nevertheless, these tools usually need implementation at the C level, whereas the design of neural networks is usually performed at a higher level (such as Keras or TensorFlow). In this paper, we propose a fully automated flow for creating a C-level implementation that is synthesizable with HLS Tools. Various aspects such as performance, minimal access to memory elements, data type knobs, and design verification are considered. Our results show that the generated C implementation is much more HLS friendly than previous works. Furthermore, a complete flow is proposed to determine different fixed-point precisions for network elements. We show that our method results in 25% and 34% reduction in bit-width for LeNet and VGG, respectively, without any accuracy loss.

Place, publisher, year, edition, pages
IEEE, 2022
Keywords
Deep Neural Network, Accelerator, High-Level Synthesis, Fixed-Point, Quantization
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-60590 (URN)10.1109/AICAS54282.2022.9869907 (DOI)000859273200032 ()2-s2.0-85139073458 (Scopus ID)978-1-6654-0996-4 (ISBN)
Conference
IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) - Intelligent Technology in the Post-Pandemic Era, JUN 13-15, 2022, Incheon, SOUTH KOREA
Available from: 2022-11-09 Created: 2022-11-09 Last updated: 2023-10-09Bibliographically approved
Riazati, M., Daneshtalab, M., Sjödin, M. & Lisper, B. (2022). DeepFlexiHLS: Deep Neural Network Flexible High-Level Synthesis Directive Generator. In: 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings: . Paper presented at 8th IEEE Nordic Circuits and Systems Conference, NORCAS 2022, 25 October 2022 through 26 October 2022. Institute of Electrical and Electronics Engineers Inc.
Open this publication in new window or tab >>DeepFlexiHLS: Deep Neural Network Flexible High-Level Synthesis Directive Generator
2022 (English)In: 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings, Institute of Electrical and Electronics Engineers Inc. , 2022Conference paper, Published paper (Refereed)
Abstract [en]

Deep Neural Networks (DNNs) are now widely adopted to solve various problems ranging from speech recognition to image classification. Since DNNs demand a large amount of processing power, their implementation on hardware, i.e., FPGA or ASIC, has received much attention. High-level synthesis is widely used since it significantly boosts productivity and flexibility and requires minimal hardware knowledge. However, when HLS transforms a C implementation to a Register-Transfer Level one, the high parallelism capability of the FPGA is not well-utilized. HLS tools provide a feature called directives through which designers can guide the tool using some defined C pragma statements to improve performance. Nevertheless, finding appropriate directives is another challenge, which needs considerable expertise and experience. This paper proposes DeepFlexiHLS, a two-stage design space exploration flow to find a set of directives to achieve minimal latency. In the first stage, a partition-based method is used to find the directives corresponding to each partition. Aggregating all these directives leads to minimal latency. Experimental results show 54% more speed-up than similar work on VGG neural network. In the second stage, an estimator is implemented to find the latency and resource utilization of various combinations of the found directives. The results form a Pareto-frontier from which the designer can choose if FPGA resources are limited or are not to be entirely used by the DNN module.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2022
Keywords
Accelerator, CNN, Deep Neural Network, Design Space Exploration, HLS, Field programmable gate arrays (FPGA), High level synthesis, Integrated circuit design, Speech recognition, High-level synthesis, Images classification, Improve performance, Large amounts, Network demands, Processing power, Register-transfer level, Two stage designs, Deep neural networks
National Category
Computer Sciences
Identifiers
urn:nbn:se:mdh:diva-61069 (URN)10.1109/NorCAS57515.2022.9934617 (DOI)000889469600019 ()2-s2.0-85142437239 (Scopus ID)9798350345506 (ISBN)
Conference
8th IEEE Nordic Circuits and Systems Conference, NORCAS 2022, 25 October 2022 through 26 October 2022
Available from: 2022-11-30 Created: 2022-11-30 Last updated: 2023-10-09Bibliographically approved
Helali Moghadam, M., Borg, M., Saadatmand, M., Mousavirad, S. J., Bohlin, M. & Lisper, B. (2022). Machine Learning Testing in an ADAS Case Study Using Simulation-Integrated Bio-Inspired Search-Based Testing.
Open this publication in new window or tab >>Machine Learning Testing in an ADAS Case Study Using Simulation-Integrated Bio-Inspired Search-Based Testing
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2022 (English)Report (Other academic)
Abstract [en]

This paper presents an extended version of Deeper, a search-based simulation-integrated test solution that generates failure-revealing test scenarios for testing a deep neural network-based lane-keeping system. In the newly proposed version, we utilize a new set of bio-inspired search algorithms, genetic algorithm (GA), (μ+ λ) and (μ,λ) evolution strategies(ES), and particle swarm optimization (PSO), that leverage a quality population seed and domain-specific crossover and mutation operations tailored for the presentation model used for modeling the test scenarios. In order to demonstrate the capabilities of the new test generators within Deeper, we carry out an empirical evaluation and comparison with regard to the results of five participating tools in the cyber-physical systems testing competition at SBST 2021. Our evaluation shows the newly proposed test generators in Deeper not only represent a considerable improvement on the previous version but also prove to be effective and efficient in provoking a considerable number of diverse failure-revealing test scenarios for testing an ML-driven lane-keeping system. They can trigger several failures while promoting test scenario diversity, under a limited test time budget, high target failure severity, and strict speed limit constraints.

Publisher
p. 20
Keywords
Machine Learning Testing, Search-Based Testing, Evolutionary Computation, Advanced Driver Assistance Systems, Deep Learning, Lane-Keeping System
National Category
Computer Sciences Software Engineering Computer Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-57607 (URN)10.48550/arXiv.2203.12026 (DOI)
Available from: 2022-03-12 Created: 2022-03-12 Last updated: 2023-09-13Bibliographically approved
Masud, A. N. & Lisper, B. (2022). On the Computation of Interprocedural Weak Control Closure. In: CC 2022 - Proceedings of the 31st ACM SIGPLAN International Conference on Compiler Construction: . Paper presented at 31st ACM SIGPLAN International Conference on Compiler Construction, CC 2022, 2 April 2022 through 3 April 2022 (pp. 65-76). Association for Computing Machinery, Inc
Open this publication in new window or tab >>On the Computation of Interprocedural Weak Control Closure
2022 (English)In: CC 2022 - Proceedings of the 31st ACM SIGPLAN International Conference on Compiler Construction, Association for Computing Machinery, Inc , 2022, p. 65-76Conference paper, Published paper (Refereed)
Abstract [en]

Many program analysis techniques depend on capturing the control dependencies of the program. Most existing control dependence algorithms either compute intraprocedural control dependencies only, or they compute control dependence relations that are not precise in general including nonterminating systems. Weak control closure (WCC) subsumes all known nontermination insensitive control dependence relations, including those that are appropriate for nonterminating systems. In this paper, we provide the first formal development of an algorithm to compute the WCC for interprocedural programs capturing the weak form of interprocedural control dependencies. The method is widely applicable due to the generality of WCC. Theorems on the theoretical results of soundness, precision, and the worst-case complexity of our method are also included. We have compared our algorithm with a WCC computation algorithm based on a state-of-The-Art interprocedural control dependence computation algorithm. The latter algorithm loses soundness, and we improve the precision by 15.21% on all our experimental benchmarks. This empirical evidence suggests that our algorithm is more effective for any client application of WCC requiring interprocedural program analysis.

Place, publisher, year, edition, pages
Association for Computing Machinery, Inc, 2022
Keywords
Control dependency, debugging, nontermination insensitive, program slicing, weak control closure, Program debugging, Computation algorithm, Dependence relation, Inter-procedural, Non terminations, Program analysis, Application programs
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:mdh:diva-58775 (URN)10.1145/3497776.3517782 (DOI)000883330900007 ()2-s2.0-85127900578 (Scopus ID)9781450391832 (ISBN)
Conference
31st ACM SIGPLAN International Conference on Compiler Construction, CC 2022, 2 April 2022 through 3 April 2022
Available from: 2022-07-13 Created: 2022-07-13 Last updated: 2022-12-15Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0001-5297-6548

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