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Publications (10 of 66) Show all publications
Desai, N., Dobrin, R. & Punnekkat, S. (2023). A Topology-specific Tight Worst-case Analysis of Strict Priority Traffic in Real-time Systems. In: IEEE Int. Conf. Emerging Technol. Factory Autom., ETFA: . Paper presented at IEEE International Conference on Emerging Technologies and Factory Automation, ETFA. Institute of Electrical and Electronics Engineers Inc.
Open this publication in new window or tab >>A Topology-specific Tight Worst-case Analysis of Strict Priority Traffic in Real-time Systems
2023 (English)In: IEEE Int. Conf. Emerging Technol. Factory Autom., ETFA, Institute of Electrical and Electronics Engineers Inc. , 2023Conference paper, Published paper (Refereed)
Abstract [en]

Tight end-to-end worst-case delay bounds for periodic traffic streams are essential for time sensitive networks. In this paper, we provide an algorithm to compute a tight (and accurate) end-to-end worst-case bound by considering distinct topological patterns and the manner in which streams enter and leave switches. This refined analysis uses non-preemptive, strict-priority arbitration mechanism commonly deployed in Ethernet switches. Compared to the state-of-the-art that considers all higher and equal priority interference as contributing to the worst-case bound, we present an analytical approach for computing a tighter worst-case delay bound and prove through discrete event simulations that only a certain number of equal-priority interference streams can actually affect the worst-case case. Our results enable efficient resource allocation and have implications for online re-configuration mechanisms for time-sensitive factory communication systems.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2023
Keywords
Real-time networks, Strict-priority traffic, TSN, Worst-case delay, Discrete event simulation, Interactive computer systems, Online systems, Topology, Bad-case delay, Delay bound, End to end, Periodic traffic, Real - Time system, Real time network, Traffic streams, Worst-case analysis, Real time systems
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:mdh:diva-64694 (URN)10.1109/ETFA54631.2023.10275348 (DOI)2-s2.0-85175426336 (Scopus ID)9798350339918 (ISBN)
Conference
IEEE International Conference on Emerging Technologies and Factory Automation, ETFA
Available from: 2023-11-09 Created: 2023-11-09 Last updated: 2023-11-09Bibliographically approved
Desai, N., Dobrin, R. & Punnekkat, S. (2022). MALOC: Building an adaptive scheduling and routing framework for rate-constrained TSN traffic. In: IEEE International Conference on Emerging Technologies and Factory Automation, ETFA: . Paper presented at 27th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2022, Stuttgart, Germany, 6-9 September 2022. Institute of Electrical and Electronics Engineers Inc.
Open this publication in new window or tab >>MALOC: Building an adaptive scheduling and routing framework for rate-constrained TSN traffic
2022 (English)In: IEEE International Conference on Emerging Technologies and Factory Automation, ETFA, Institute of Electrical and Electronics Engineers Inc. , 2022Conference paper, Published paper (Refereed)
Abstract [en]

Time Sensitive Networking (TSN) is a set of standards aimed at providing real-time guarantees over existing Ethernet standards. Worst-case traversal time (WCTT) analyses of network traffic are traditionally used in schedulability and routing analyses to determine feasible routes for traffic streams. However, worst-case conditions happen quite rarely from a probabilistic perspective. The typical or average-case traversal times are easier to compute and can be used as an effective design tool for routing and scheduling. In this paper, we present "MaLoC"or Maximally Loaded Common links for routing and scheduling of rate-constrained (RC) traffic in time-sensitive networks (TSN). The proposed framework employs a fully decentralized approach to route and schedule generation with only switch-local information. We further provide a preliminary evaluation of the proposed approach using a simple network topology.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2022
Keywords
Adaptivity, Online routing, Rate-constrained traffic, Scheduling, TSN, Network routing, Adaptive routing, Adaptive scheduling, Routing and scheduling, Scheduling and routing, Time sensitive networking, Traversal time, Network topology
National Category
Computer Sciences
Identifiers
urn:nbn:se:mdh:diva-60955 (URN)10.1109/ETFA52439.2022.9921474 (DOI)000934103900051 ()2-s2.0-85141393809 (Scopus ID)9781665499965 (ISBN)
Conference
27th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2022, Stuttgart, Germany, 6-9 September 2022
Available from: 2022-11-22 Created: 2022-11-22 Last updated: 2023-03-22Bibliographically approved
Stavrakakis, I., Gordon, D., Tierney, B., Becevel, A., Murphy, E., Dodig-Crnkovic, G., . . . O'Sullivan, D. (2022). The teaching of computer ethics on computer science and related degree programmes. a European survey. INTERNATIONAL JOURNAL OF ETHICS EDUCATION, 7(1), 101-129
Open this publication in new window or tab >>The teaching of computer ethics on computer science and related degree programmes. a European survey
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2022 (English)In: INTERNATIONAL JOURNAL OF ETHICS EDUCATION, ISSN 2363-9997, Vol. 7, no 1, p. 101-129Article in journal (Refereed) Published
Abstract [en]

Within the Computer Science community, many ethical issues have emerged as significant and critical concerns. Computer ethics is an academic field in its own right and there are unique ethical issues associated with information technology. It encompasses a range of issues and concerns including privacy and agency around personal information, Artificial Intelligence and pervasive technology, the Internet of Things and surveillance applications. As computing technology impacts society at an ever growing pace, there are growing calls for more computer ethics content to be included in Computer Science curricula. In this paper we present the results of a survey that polled faculty from Computer Science and related disciplines about teaching practices for computer ethics at their institutions. The survey was completed by respondents from 61 universities across 23 European countries. Participants were surveyed on whether or not computer ethics is taught to Computer Science students at each institution, the reasons why computer ethics is or is not taught, how computer ethics is taught, the background of staff who teach computer ethics and the scope of computer ethics curricula. This paper presents and discusses the results of the survey.

Place, publisher, year, edition, pages
SPRINGERNATURE, 2022
Keywords
Ethics, Computer Ethics, Teaching Computer Ethics, Computer Science Education
National Category
Educational Sciences
Identifiers
urn:nbn:se:mdh:diva-56310 (URN)10.1007/s40889-021-00135-1 (DOI)000705708600001 ()
Available from: 2021-10-28 Created: 2021-10-28 Last updated: 2022-08-29Bibliographically approved
Markovic, F., Carlson, J. & Dobrin, R. (2020). Cache-aware response time analysis for real-time tasks with fixed preemption points. In: The 26TH IEEE Real-time and embedded Technology and Applications Symposium RTAS'20: . Paper presented at The 26TH IEEE Real-time and embedded Technology and Applications Symposium RTAS'20, 21 Apr 2020, Sydney, Australia (pp. 30-42). Sydney, Australia: Institute of Electrical and Electronics Engineers (IEEE), Article ID 9113116.
Open this publication in new window or tab >>Cache-aware response time analysis for real-time tasks with fixed preemption points
2020 (English)In: The 26TH IEEE Real-time and embedded Technology and Applications Symposium RTAS'20, Sydney, Australia: Institute of Electrical and Electronics Engineers (IEEE), 2020, p. 30-42, article id 9113116Conference paper, Published paper (Other academic)
Abstract [en]

In real-time systems that employ preemptive scheduling and cache architecture, it is essential to account as precisely as possible for cache-related preemption delays in the schedulability analysis, as an imprecise estimation may falsely deem the system unschedulable. In the current state of the art for preemptive scheduling of tasks with fixed preemption points, the existing schedulability analysis considers overly pessimistic estimation of cache-related preemption delay, which eventually leads to overly pessimistic schedulability results. In this paper, we propose a novel response time analysis for real-time tasks with fixed preemption points, accounting for a more precise estimation of cache-related preemption delays. The evaluation shows that the proposed analysis significantly dominates the existing approach by being able to always identify more schedulable tasksets.

Place, publisher, year, edition, pages
Sydney, Australia: Institute of Electrical and Electronics Engineers (IEEE), 2020
Keywords
Real-time Systems, Cache-related preemptiondelay (CRPD), Fixed-Priority scheduling, Preemptive Scheduling, Cache Memory
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-47343 (URN)10.1109/RTAS48715.2020.00-19 (DOI)000713963100002 ()2-s2.0-85086755759 (Scopus ID)
Conference
The 26TH IEEE Real-time and embedded Technology and Applications Symposium RTAS'20, 21 Apr 2020, Sydney, Australia
Available from: 2020-04-24 Created: 2020-04-24 Last updated: 2022-11-08Bibliographically approved
Markovic, F., Carlson, J., Altmeyer, S. & Dobrin, R. (2020). Improving the accuracy of cache-aware response time analysis using preemption partitioning. In: Leibniz International Proceedings in Informatics, LIPIcs: . Paper presented at 32nd Euromicro Conference on Real-Time Systems, ECRTS 2020; Virtual, Online; 7 July 2020 through 10 July 2020; Code 161972. , 165, Article ID 5.
Open this publication in new window or tab >>Improving the accuracy of cache-aware response time analysis using preemption partitioning
2020 (English)In: Leibniz International Proceedings in Informatics, LIPIcs, 2020, Vol. 165, article id 5Conference paper, Published paper (Refereed)
Abstract [en]

Schedulability analyses for preemptive real-time systems need to take into account cache-related preemption delays (CRPD) caused by preemptions between the tasks. The estimation of the CRPD values must be sound, i.e. it must not be lower than the worst-case CRPD that may occur at runtime, but also should minimise the pessimism of estimation. The existing methods over-approximate the computed CRPD upper bounds by accounting for multiple preemption combinations which cannot occur simultaneously during runtime. This over-approximation may further lead to the over-approximation of the worst-case response times of the tasks, and therefore a false-negative estimation of the system’s schedulability. In this paper, we propose a more precise cache-aware response time analysis for sporadic real-time systems under fully-preemptive fixed priority scheduling. The evaluation shows a significant improvement over the existing state of the art approaches.

Series
Leibniz International Proceedings in Informatics, ISSN 1868-8969
Keywords
Real-time systems, Fixed-Priority Preemptive Scheduling, Preemption delay, Cache memory, Schedulability
National Category
Engineering and Technology Computer Systems
Identifiers
urn:nbn:se:mdh:diva-49330 (URN)10.4230/LIPIcs.ECRTS.2020.5 (DOI)2-s2.0-85090273209 (Scopus ID)978-3-95977-152-8 (ISBN)
Conference
32nd Euromicro Conference on Real-Time Systems, ECRTS 2020; Virtual, Online; 7 July 2020 through 10 July 2020; Code 161972
Available from: 2020-07-08 Created: 2020-07-08 Last updated: 2023-09-13Bibliographically approved
Markovic, F., Carlson, J. & Dobrin, R. (2019). A Comparison of Partitioning Strategies for Fixed Points-based Limited Preemptive Scheduling. IEEE Transactions on Industrial Informatics, 15(2), 1070-1081
Open this publication in new window or tab >>A Comparison of Partitioning Strategies for Fixed Points-based Limited Preemptive Scheduling
2019 (English)In: IEEE Transactions on Industrial Informatics, ISSN 1551-3203, E-ISSN 1941-0050, Vol. 15, no 2, p. 1070-1081Article in journal (Refereed) Published
Abstract [en]

The increasing industrial demand for handling complex functionalities has influenced the design of hardware architectures for time critical embedded systems, during the past decade. Multi-core systems facilitate the inclusion of many complex functionalities, while, at the same time, inducing cache related overheads, as well as adding partitioning complexity to the overall system schedulability. One of the efficient paradigms for controlling and reducing the cache related costs in real-time systems is Limited Preemptive Scheduling (LPS), with its particular instance Fixed Preemption Points Scheduling (LP-FPPS), that has been shown to outperform other alternatives as well as has been supported by and investigated in the automotive domain. With respect to the partitioning constraints, Partitioned Scheduling has been widely used to pre-runtime allocate tasks to specific cores, resulting in a predictable cache-related preemption delays estimations. In this paper we propose to integrate LP-FPPS and Partitioned Scheduling on fixed-priority multicore real-time systems in order to increase the overall system schedulability.We define a new joint approach for task partitioning and preemption point selection, that is based on the computation of the maximum blocking tolerance upon each allocation, thus being able to quantify the schedulability of the taskset on each processor. Furthermore, we investigate partitioning strategies based on different heuristics, i.e. First Fit Decreasing and Worst Fit Decreasing, and priority and density taskset orderings. The evaluation performed on randomly generated tasksets shows that in the general case, no single partitioning strategy fully dominates the others. However, the evaluation results reveal that certain partitioning strategies perform significantly better with respect to the overall schedulability for specific taskset characteristics. The results also reveal that the proposed partitioning strategies outperform Fully Preemptive and Non-Preemptive partitioned scheduling in terms of successful partitioning.

Keywords
Real-Time Systems, Partitioned Scheduling, Limited Preemptive Scheduling, Fixed Preemption Points
National Category
Computer Sciences
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-39827 (URN)10.1109/TII.2018.2848879 (DOI)000458199000043 ()2-s2.0-85048607044 (Scopus ID)
Available from: 2018-06-14 Created: 2018-06-14 Last updated: 2019-02-28Bibliographically approved
Dobrin, R., Desai, N. & Punnekkat, S. (2019). On fault-tolerant scheduling of time sensitive networks. In: OpenAccess Series in Informatics: . Paper presented at 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems, CERTS 2019, 9 July 2019. Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing
Open this publication in new window or tab >>On fault-tolerant scheduling of time sensitive networks
2019 (English)In: OpenAccess Series in Informatics, Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing , 2019Conference paper, Published paper (Refereed)
Abstract [en]

Time sensitive networking (TSN) is gaining attention in industrial automation networks since it brings essential real-time capabilities at the data link layer. Though it can provide deterministic latency under error free conditions, TSN still largely depends on space redundancy for improved reliability. In many scenarios, time redundancy could be an adequate as well as cost efficient alternative. Time redundancy in turn will have implications due to the need for over-provisions needed for timeliness guarantees. In this paper, we discuss how to embed fault-tolerance capability into TSN schedules and describe our approach using a simple example.

Place, publisher, year, edition, pages
Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing, 2019
Keywords
Fault-tolerant schedule, Time redundancy, Time sensitive networks(TSN), Embedded systems, Fault tolerance, Interactive computer systems, Redundancy, Data link layer, Fault tolerant scheduling, Fault-tolerance capability, Fault-tolerant, Industrial automation, Real time capability, Real time systems
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-46541 (URN)10.4230/OASIcs.CERTS.2019.5 (DOI)2-s2.0-85070896705 (Scopus ID)9783959771191 (ISBN)
Conference
4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems, CERTS 2019, 9 July 2019
Available from: 2019-12-17 Created: 2019-12-17 Last updated: 2021-10-29Bibliographically approved
Davis, R., Thekilakkattil, A., Gettings, O., Dobrin, R., Punnekkat, S. & Chen, J.-J. (2018). Exact Speedup Factors and Sub-Optimality for Non-Preemptive Scheduling. Real-time systems, 208-246
Open this publication in new window or tab >>Exact Speedup Factors and Sub-Optimality for Non-Preemptive Scheduling
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2018 (English)In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, p. 208-246Article in journal (Refereed) Published
Abstract [en]

Fixed priority scheduling is used in many real-time systems; however, both preemptive and non-preemptive variants (FP-P and FP-NP) are known to be sub-optimal when compared to an optimal uniprocessor scheduling algorithm such as preemptive Earliest Deadline First (EDF-P). In this paper, we investigate the sub-optimality of xed priority non-preemptive scheduling. Speci cally, we derive the exact processor speed-up factor required to guarantee the feasibility under FP-NP (i.e. schedulablability assuming an optimal priority assignment) of any task set that is feasible under EDF-P. As a consequence of this work, we also derive a lower bound on the sub-optimality of non-preemptive EDF (EDF-NP). As this lower bound matches a recently published upper bound for the same quantity, it closes the exact sub-optimality for EDF-NP. It is known that neither preemptive, nor non-preemptive xed priority scheduling dominates the other, in other words, there are task sets that are feasible on a processor of unit speed under FP-P that are not feasible under FP-NP and vice-versa. Hence comparing these two algorithms, there are non-trivial speedup factors in both directions. We derive the exact speed-up factor required to guarantee the FP-NP feasibility of any FP-P feasible task set. Further, we derive the exact speed-up factor required to guarantee FP-P feasibility of any constrained-deadline FP-NP feasible task set.

Keywords
real-time uniprocessor resource augmentation speedupfactor sub-optimality non-preemptive scheduling preemptive scheduling EDF xed priority
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-37337 (URN)10.1007/s11241-017-9294-3 (DOI)000419955500007 ()2-s2.0-85032335776 (Scopus ID)
Available from: 2017-11-28 Created: 2017-11-28 Last updated: 2018-01-26Bibliographically approved
Markovic, F., Carlson, J., Thekilakkattil, A., Dobrin, R. & Lisper, B. (2018). Probabilistic Response Time Analysis for Fixed Preemption Point Selection. In: 13th International Symposium on Industrial Embedded Systems SIES '18: . Paper presented at 13th International Symposium on Industrial Embedded Systems SIES '18, 06 Jun 2018, Graz, Austria. , Article ID 8442099.
Open this publication in new window or tab >>Probabilistic Response Time Analysis for Fixed Preemption Point Selection
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2018 (English)In: 13th International Symposium on Industrial Embedded Systems SIES '18, 2018, article id 8442099Conference paper, Published paper (Refereed)
Abstract [en]

Preemption point selection has a significant impact on the schedulability of Real-Time tasks under the Fixed Preemption Point approach in Limited Preemptive Scheduling. Many real time systems can occasionally tolerate deadline misses as long as their occurrence does not exceed a specified probabilistic threshold. However, the existing approaches for preemption point selection are inappropriate for such systems, as they are mainly aiming to provide hard guarantees, considering worst case (upper bounded) preemption overheads. Additionally, the worst case preemption overheads typically occur with very low probabilities. In this paper, we propose a novel preemption point selection approach, and an associated probabilistic response time analysis, considering preemption related overheads modelled as probabilistic distributions. The method is suitable for providing solutions in systems that can occasionally tolerate deadline misses and can be interesting in the context of mixed criticality systems. Our method is able to find solutions, in terms of preemption point selections, in all cases where the existing approaches do. Moreover, it provides preemption point selections for additional tasksets that guarantees the overall taskset schedulability with a certain probability. The evaluation results show an improvement with respect to increasing the number of tasksets for which a preemption point selection is possible compared to existing, upper-bound based, selection approaches. The results show that the deadline miss probabilities of the tasksets and associated preemption point selections are considerably low.

Keywords
Real-time systems, Limited Preemptive Scheduling, Fixed Preemption Points Scheduling, Probabilistic Response Time Analysis, Preemption Point Selection
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-39256 (URN)10.1109/SIES.2018.8442099 (DOI)000520083700016 ()2-s2.0-85053475648 (Scopus ID)9781538641552 (ISBN)
Conference
13th International Symposium on Industrial Embedded Systems SIES '18, 06 Jun 2018, Graz, Austria
Available from: 2018-05-23 Created: 2018-05-23 Last updated: 2022-11-08Bibliographically approved
Aravind, M., Wiklander, G., Palmheden, J. & Dobrin, R. (2017). An Event-Based Messaging Architecture for Vehicular Internet of Things (IoT) Platforms. In: Communications in Computer and Information Science, vol. 778: . Paper presented at 9th International Conference on Data-Driven Innovation, ICT Innovations 2017; Skopje; Macedonia; 18 September 2017 through 23 September 2017 (pp. 37-46). Springer Verlag
Open this publication in new window or tab >>An Event-Based Messaging Architecture for Vehicular Internet of Things (IoT) Platforms
2017 (English)In: Communications in Computer and Information Science, vol. 778, Springer Verlag , 2017, p. 37-46Conference paper, Published paper (Refereed)
Abstract [en]

Internet of Things (IoT) has revolutionized transportation systems by connecting vehicles consequently enabling their tracking, as well as monitoring of driver activities. Such an IoT platform requires a significant amount of data to be send from the on-board vehicle to the off-board servers, contributing to high network usage. The data can be send at regular intervals or in an event-based manner whenever relevant events occur. In interval-based approach, the data is send even if it is not relevant for reporting leading to a wastage of network resources, e.g., when the data does not change considerably compared to the previously sent value. In this paper, we investigate the possibility of using an event-based architecture to send data from the on-board system to the off-board system. The results show that our event-based architecture improves the accuracy of data available at the off-board system, by a careful selection of events. Moreover, we found that our event based architecture significantly decreases the frequency of sending messages, particularly during highway driving, leading to reduced average data transfer rates. Our results enable a customer to perform trade-offs between accuracy and data transfer rates. 

Place, publisher, year, edition, pages
Springer Verlag, 2017
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-36678 (URN)10.1007/978-3-319-67597-8_4 (DOI)000578460600004 ()2-s2.0-85029783908 (Scopus ID)9783319675961 (ISBN)
Conference
9th International Conference on Data-Driven Innovation, ICT Innovations 2017; Skopje; Macedonia; 18 September 2017 through 23 September 2017
Available from: 2017-10-06 Created: 2017-10-06 Last updated: 2020-11-13Bibliographically approved
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ORCID iD: ORCID iD iconorcid.org/0000-0003-4157-3537

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