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Strandberg, P. E., Enoiu, E. P., Afzal, W., Daniel, S. & Feldt, R. (2019). Information Flow in Software Testing: An Interview Study with Embedded Software Engineering Practitioners. IEEE Access, 7, 46434-46453
Open this publication in new window or tab >>Information Flow in Software Testing: An Interview Study with Embedded Software Engineering Practitioners
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2019 (English)In: IEEE Access, E-ISSN 2169-3536, Vol. 7, p. 46434-46453Article in journal (Refereed) Published
Abstract [en]

Activities in software testing is a challenge for companies that develop embedded systems where multiple functional teams and technologically difficult tasks are common. This study aims at exploring the information flow in software testing, the perceived challenges and good approaches, for a more effective information flow. We conducted semi-structured interviews with twelve software practitioners working at five organizations in the embedded software industry in Sweden. The interviews were analyzed by means of thematic analysis. The data was classified into six themes that affect the information flow in software testing: testing and troubleshooting, communication, processes, technology, artifacts and organization. We further identified a number of challenges such as poor feedback and understanding exactly what has been tested; and approaches such as fast feedback as well as custom automated test reporting; to achieve an improved information flow. Our results indicate that there are many opportunities to improve this information flow: a first mitigation step is to better understand the challenges and approaches. Future work is needed to realize this in practice, for example to shorten feedback cycles between roles, as well as enhance exploration and visualization of test results

National Category
Software Engineering
Identifiers
urn:nbn:se:mdh:diva-40930 (URN)10.1109/ACCESS.2019.2909093 (DOI)000465621200001 ()2-s2.0-85064750453 (Scopus ID)
Funder
Knowledge Foundation, 20150277
Available from: 2018-09-13 Created: 2018-09-13 Last updated: 2019-05-09Bibliographically approved
Abbas, M., Inayat, I., Jan, N., Saadatmand, M., Enoiu, E. P. & Daniel, S. (2019). MBRP: Model-based Requirements Prioritization Using PageRank Algorithm. In: Asia-Pacific Software Engineering Conference APSEC 2019: . Paper presented at Asia-Pacific Software Engineering Conference APSEC 2019, 02 Dec 2019, Putrajaya, Malaysia. Putrajaya, Malaysia
Open this publication in new window or tab >>MBRP: Model-based Requirements Prioritization Using PageRank Algorithm
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2019 (English)In: Asia-Pacific Software Engineering Conference APSEC 2019, Putrajaya, Malaysia, 2019Conference paper, Published paper (Refereed)
Abstract [en]

Requirements prioritization plays an important role in driving project success during software development. Literature reveals that existing requirements prioritization approaches ignore vital factors such as interdependency between requirements. Existing requirements prioritization approaches are also generally time-consuming and involve substantial manual effort. Besides, these approaches show substantial limitations in terms of the number of requirements under consideration. There is some evidence suggesting that models could have a useful role in the analysis of requirements interdependency and their visualization, contributing towards the improvement of the overall requirements prioritization process. However, to date, just a handful of studies are focused on model-based strategies for requirements prioritization, considering only conflict-free functional requirements. This paper uses a meta-model-based approach to help the requirements analyst to model the requirements, stakeholders, and inter-dependencies between requirements. The model instance is then processed by our modified PageRank algorithm to prioritize the given requirements. An experiment was conducted, comparing our modified PageRank algorithm’s efficiency and accuracy with five existing requirements prioritization methods. Besides, we also compared our results with a baseline prioritized list of 104 requirements prepared by 28 graduate students. Our results show that our modified PageRank algorithm was able to prioritize the requirements more effectively and efficiently than the other prioritization methods.

Place, publisher, year, edition, pages
Putrajaya, Malaysia: , 2019
Keywords
requirement prioritization, requirements interdependencies, meta-model, page-rank
National Category
Engineering and Technology Computer Systems
Identifiers
urn:nbn:se:mdh:diva-45498 (URN)
Conference
Asia-Pacific Software Engineering Conference APSEC 2019, 02 Dec 2019, Putrajaya, Malaysia
Projects
ARRAY - Automation Region Research AcademyXIVT - eXcellence in Variant Testing
Available from: 2019-10-28 Created: 2019-10-28 Last updated: 2019-10-28Bibliographically approved
Abbaspour Asadollah, S., Daniel, S., Eldh, S. & Hansson, H. (2018). A Runtime Verification Tool for Detecting Concurrency Bugs in FreeRTOS Embedded Software. In: Proceedings - 17th International Symposium on Parallel and Distributed Computing, ISPDC 2018: . Paper presented at 17th International Symposium on Parallel and Distributed Computing, ISPDC 2018, 25 June 2018 through 28 June 2018 (pp. 172-179). Institute of Electrical and Electronics Engineers Inc., Article ID 8452035.
Open this publication in new window or tab >>A Runtime Verification Tool for Detecting Concurrency Bugs in FreeRTOS Embedded Software
2018 (English)In: Proceedings - 17th International Symposium on Parallel and Distributed Computing, ISPDC 2018, Institute of Electrical and Electronics Engineers Inc. , 2018, p. 172-179, article id 8452035Conference paper, Published paper (Refereed)
Abstract [en]

This article presents a runtime verification tool for embedded software executing under the open source real-time operating system FreeRTOS. The tool detects and diagnoses concurrency bugs such as deadlock, starvation, and suspension based-locking. The tool finds concurrency bugs at runtime without debugging and tracing the source code. The tool uses the Tracealyzer tool for logging relevant events. Analysing the logs, our tool can detect the concurrency bugs by applying algorithms for diagnosing each concurrency bug type individually. In this paper, we present the implementation of the tool, as well as its functional architecture, together with illustration of its use. The tool can be used during program testing to gain interesting information about embedded software executions. We present initial results of running the tool on some classical bug examples running on an AVR 32-bit board SAM4S. 

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2018
Series
International Symposium on Parallel and Distributed Computing
Keywords
Bug Detector, Concurrency Bugs, Embedded Software, FreeRTOS, Runtime Verification Tool, Computer operating systems, Distributed computer systems, Locks (fasteners), Open source software, Open systems, Program diagnostics, Software testing, Verification, Functional architecture, Interesting information, Real time operating system, Run-time verification, Software execution, Program debugging
National Category
Embedded Systems Computer Systems
Identifiers
urn:nbn:se:mdh:diva-41125 (URN)10.1109/ISPDC2018.2018.00032 (DOI)000447280800023 ()2-s2.0-85053906243 (Scopus ID)9781538653302 (ISBN)
Conference
17th International Symposium on Parallel and Distributed Computing, ISPDC 2018, 25 June 2018 through 28 June 2018
Available from: 2018-10-10 Created: 2018-10-10 Last updated: 2018-10-25Bibliographically approved
Strandberg, P. E., Ostrand, T. J., WEYUKER, E., Daniel, S. & Afzal, W. (2018). Automated test mapping and coverage for network topologies. In: ISSTA 2018 - Proceedings of the 27th ACM SIGSOFT International Symposium on Software Testing and Analysis: . Paper presented at 27th ACM SIGSOFT International Symposium on Software Testing and Analysis, ISSTA 2018, 16 July 2018 through 21 July 2018 (pp. 73-83). Association for Computing Machinery, Inc
Open this publication in new window or tab >>Automated test mapping and coverage for network topologies
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2018 (English)In: ISSTA 2018 - Proceedings of the 27th ACM SIGSOFT International Symposium on Software Testing and Analysis, Association for Computing Machinery, Inc , 2018, p. 73-83Conference paper, Published paper (Refereed)
Abstract [en]

Communication devices such as routers and switches play a critical role in the reliable functioning of embedded system networks. Dozens of such devices may be part of an embedded system network, and they need to be tested in conjunction with various computational elements on actual hardware, in many different configurations that are representative of actual operating networks. An individual physical network topology can be used as the basis for a test system that can execute many test cases, by identifying the part of the physical network topology that corresponds to the configuration required by each individual test case. Given a set of available test systems and a large number of test cases, the problem is to determine for each test case, which of the test systems are suitable for executing the test case, and to provide the mapping that associates the test case elements (the logical network topology) with the appropriate elements of the test system (the physical network topology). We studied a real industrial environment where this problem was originally handled by a simple software procedure that was very slow in many cases, and also failed to provide thorough coverage of each network's elements. In this paper, we represent both the test systems and the test cases as graphs, and develop a new prototype algorithm that a) determines whether or not a test case can be mapped to a subgraph of the test system, b) rapidly finds mappings that do exist, and c) exercises diverse sets of network nodes when multiple mappings exist for the test case. The prototype has been implemented and applied to over 10,000 combinations of test cases and test systems, and reduced the computation time by a factor of more than 80 from the original procedure. In addition, relative to a meaningful measure of network topology coverage, the mappings achieved an increased level of thoroughness in exercising the elements of each test system.

Place, publisher, year, edition, pages
Association for Computing Machinery, Inc, 2018
Keywords
Network topology, Subgraph isomorphism, Test coverage, Testing, Embedded systems, Mapping, Test facilities, Topology, Communication device, Computational elements, Industrial environments, Physical network topologies, Prototype algorithms, Software testing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-40528 (URN)10.1145/3213846.3213859 (DOI)2-s2.0-85051515196 (Scopus ID)9781450356992 (ISBN)
Conference
27th ACM SIGSOFT International Symposium on Software Testing and Analysis, ISSTA 2018, 16 July 2018 through 21 July 2018
Available from: 2018-08-23 Created: 2018-08-23 Last updated: 2018-10-02Bibliographically approved
Strandberg, P. E., Afzal, W. & Daniel, S. (2018). Decision Making and Visualizations Based on Test Results. In: Empirical Software Engineering and Measurement, 12th International Symposium on ESEM18: . Paper presented at Empirical Software Engineering and Measurement, 12th International Symposium on ESEM18, 11 Oct 2018, Oulu, Finland. , Article ID 34.
Open this publication in new window or tab >>Decision Making and Visualizations Based on Test Results
2018 (English)In: Empirical Software Engineering and Measurement, 12th International Symposium on ESEM18, 2018, article id 34Conference paper, Published paper (Refereed)
Abstract [en]

Background: Testing is one of the main methods for quality assurance in the development of embedded software, as well as in software engineering in general. Consequently, test results (and how they are reported and visualized) may substantially influence business decisions in software-intensive organizations. Aims: This case study examines the role of test results from automated nightly software testing and the visualizations for decision making they enable at an embedded systems company in Sweden. In particular, we want to identify the use of the visualizations for supporting decisions from three aspects: in daily work, at feature branch merge, and at release time. Method: We conducted an embedded case study with multiple units of analysis by conducting interviews, questionnaires, using archival data and participant observations. Results: Several visualizations and reports built on top of the test results database are utilized in supporting daily work, merging a feature branch to the master and at release time. Some important visualizations are: lists of failing test cases, easy access to log files, and heatmap trend plots. The industrial practitioners perceived the visualizations and reporting as valuable, however they also mentioned several areas of improvement such as better ways of visualizing test coverage in a functional area as well as better navigation between different views. Conclusions: We conclude that visualizations of test results are a vital decision making tool for a variety of roles and tasks in embedded software development, however the visualizations need to be continuously improved to keep their value for its stakeholders.

Keywords
Software Testing, Visualizations, Decision Making
National Category
Engineering and Technology Computer Systems
Identifiers
urn:nbn:se:mdh:diva-40902 (URN)10.1145/3239235.3268921 (DOI)000469776800034 ()2-s2.0-85053207166 (Scopus ID)978-1-4503-5823-1 (ISBN)
Conference
Empirical Software Engineering and Measurement, 12th International Symposium on ESEM18, 11 Oct 2018, Oulu, Finland
Projects
TOCSYC - Testing of Critical System Characteristics (KKS)The Volvo chair of vehicular electronics and software architectureITS ESS-H Industrial Graduate School in Reliable Embedded Sensor SystemsTESTMINE - Mining Test Evolution for Improved Software Regression Test Selection (KKS)
Available from: 2018-09-13 Created: 2018-09-13 Last updated: 2019-06-18Bibliographically approved
Flemström, D., Enoiu, E. P., Afzal, W., Daniel, S., Gustafsson, T. & Kobetski, A. (2018). From natural language requirements to passive test cases using guarded assertions. In: Proceedings - 2018 IEEE 18th International Conference on Software Quality, Reliability, and Security, QRS 2018: . Paper presented at 18th IEEE International Conference on Software Quality, Reliability, and Security, QRS 2018, 16 July 2018 through 20 July 2018 (pp. 470-481). Institute of Electrical and Electronics Engineers Inc.
Open this publication in new window or tab >>From natural language requirements to passive test cases using guarded assertions
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2018 (English)In: Proceedings - 2018 IEEE 18th International Conference on Software Quality, Reliability, and Security, QRS 2018, Institute of Electrical and Electronics Engineers Inc. , 2018, p. 470-481Conference paper, Published paper (Refereed)
Abstract [en]

In large-scale embedded system development, requirements are often expressed in natural language. Translating these requirements to executable test cases, while keeping the test cases and requirements aligned, is a challenging task. While such a transformation typically requires extensive domain knowledge, we show that a systematic process in combination with passive testing would facilitate the translation as well as linking the requirements to tests. Passive testing approaches observe the behavior of the system and test their correctness without interfering with the normal behavior. We use a specific approach to passive testing: guarded assertions (G/A). This paper presents a method for transforming system requirements expressed in natural language into G/As. We further present a proof of concept evaluation, performed at Bombardier Transportation Sweden AB, in which we show how the process would be used, together with practical advice of the reasoning behind the translation steps.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2018
Keywords
Computer software selection and evaluation, Embedded systems, Natural language processing systems, Software reliability, Bombardier Transportation, Domain knowledge, Large scale embedded systems, Natural language requirements, Natural languages, Proof of concept, System requirements, Systematic process, Translation (languages)
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:mdh:diva-40744 (URN)10.1109/QRS.2018.00060 (DOI)2-s2.0-85052319900 (Scopus ID)9781538677575 (ISBN)
Conference
18th IEEE International Conference on Software Quality, Reliability, and Security, QRS 2018, 16 July 2018 through 20 July 2018
Available from: 2018-09-07 Created: 2018-09-07 Last updated: 2018-10-31Bibliographically approved
Bilic, D., Daniel, S., Afzal, W., Wallin, P., Causevic, A. & Amlinger, C. (2018). Model-Based Product Line Engineering in an Industrial Automotive Context: An Exploratory Case Study. In: 1st Intl. Workshop on Variability and Evolution of Software-intensive Systems VariVolution'18: . Paper presented at 1st Intl. Workshop on Variability and Evolution of Software-intensive Systems VariVolution'18, 10 Sep 2018, Gothenburg, Sweden.
Open this publication in new window or tab >>Model-Based Product Line Engineering in an Industrial Automotive Context: An Exploratory Case Study
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2018 (English)In: 1st Intl. Workshop on Variability and Evolution of Software-intensive Systems VariVolution'18, 2018Conference paper, Published paper (Refereed)
Abstract [en]

Product Line Engineering is an approach to reuse assets of complex systems by taking advantage of commonalities between product families. Reuse within complex systems usually means reuse of artifacts from different engineering domains such as mechanical, electronics and software engineering. Model-based systems engineering is becoming a standard for systems engineering and collaboration within different domains. This paper presents an exploratory case study on initial efforts of adopting Product Line Engineering practices within the model-based systems engineering process at Volvo Construction Equipment (Volvo CE), Sweden. We have used SysML to create overloaded models of the engine systems at Volvo CE. The variability within the engine systems was captured by using the Orthogonal Variability Modeling language. The case study has shown us that overloaded SysML models tend to become complex even on small scale systems, which in turn makes scalability of the approach a major challenge. For successful reuse and to, possibly, tackle scalability, it is necessary to have a database of reusable assets from which product variants can be derived.

Keywords
System product lines, Model-based systems engineering, Variability management, Orthogonal variability modeling
National Category
Engineering and Technology Computer Systems
Identifiers
urn:nbn:se:mdh:diva-42238 (URN)10.1145/3236405.3237200 (DOI)000455363200013 ()
Conference
1st Intl. Workshop on Variability and Evolution of Software-intensive Systems VariVolution'18, 10 Sep 2018, Gothenburg, Sweden
Projects
MegaMaRt2 - Megamodelling at Runtime (ECSEL/Vinnova)
Available from: 2018-12-28 Created: 2018-12-28 Last updated: 2019-03-29Bibliographically approved
Brahneborg, D., Afzal, W., Causevic, A., Daniel, S. & Björkman, M. (2018). Round-Trip Time Anomaly Detection. In: ICPE '18 Proceedings of the 2018 ACM/SPEC International Conference on Performance Engineering: . Paper presented at 2018 ACM/SPEC International Conference on Performance Engineering, Berlin, Germany — April 09 - 13, 2018 (pp. 107-114).
Open this publication in new window or tab >>Round-Trip Time Anomaly Detection
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2018 (English)In: ICPE '18 Proceedings of the 2018 ACM/SPEC International Conference on Performance Engineering, 2018, p. 107-114Conference paper, Published paper (Refereed)
Abstract [en]

Mobile text messages (SMS) are sometimes used for authentication, which requires short and reliable delivery times. The observed round-trip times when sending an SMS message provide valuable information on the quality of the connection. In this industry paper, we propose a method for detecting round-trip time anomalies, where the exact distribution is unknown, the variance is several orders of magnitude, and there are lots of shorter spikes that should be ignored. In particular, we show that using an adaption of Double Seasonal Exponential Smoothing to reduce the content dependent variations, followed by the Remedian to find short-term and long-term medians, successfully identifies larger groups of outliers. As training data for our method we use log files from a live SMS gateway. In order to verify the effectiveness of our approach, we utilize simulated data. Our contributions are a description on how to isolate content dependent variations, and the sequence of steps to find significant anomalies in big data.

National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-41840 (URN)10.1145/3184407.3184436 (DOI)2-s2.0-85048196185 (Scopus ID)978-1-4503-5095-2 (ISBN)
Conference
2018 ACM/SPEC International Conference on Performance Engineering, Berlin, Germany — April 09 - 13, 2018
Available from: 2018-12-27 Created: 2018-12-27 Last updated: 2018-12-27Bibliographically approved
Flemström, D., Pasqualina, P., Daniel, S., Afzal, W. & Bohlin, M. (2018). Similarity-Based Prioritization of Test Case Automation. Software quality journal, 26(4), 1421-1449
Open this publication in new window or tab >>Similarity-Based Prioritization of Test Case Automation
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2018 (English)In: Software quality journal, ISSN 0963-9314, E-ISSN 1573-1367, Vol. 26, no 4, p. 1421-1449Article in journal (Refereed) Published
Abstract [en]

The importance of efficient software testing procedures is driven by an ever increasing system complexity as well as global competition. In the particular case of manual test cases at the system integration level, where thousands of test cases may be executed before release, time must be well spent in order to test the system as completely and as efficiently as possible. Automating a subset of the manual test cases, i.e, translating the manual instructions to automatically executable code, is one way of decreasing the test effort. It is further common that test cases exhibit similarities, which can be exploited through reuse when automating a test suite. In this paper, we investigate the potential for reducing test effort by ordering the test cases before such automation, given that we can reuse already automated parts of test cases. In our analysis, we investigate several approaches for prioritization in a case study at a large Swedish vehicular manufacturer. The study analyzes the effects with respect to test effort, on four projects with a total of 3919 integration test cases constituting 35,180 test steps, written in natural language. The results show that for the four projects considered, the difference in expected manual effort between the best and the worst order found is on average 12 percentage points. The results also show that our proposed prioritization method is nearly as good as more resource demanding meta-heuristic approaches at a fraction of the computational time. Based on our results, we conclude that the order of automation is important when the set of test cases contain similar steps (instructions) that cannot be removed, but are possible to reuse. More precisely, the order is important with respect to how quickly the manual test execution effort decreases for a set of test cases that are being automated.

National Category
Software Engineering
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-35055 (URN)10.1007/s11219-017-9401-7 (DOI)000448856400008 ()2-s2.0-85043389019 (Scopus ID)
Projects
IMPRINT
Funder
Vinnova, 2014-03397Knowledge Foundation, 20130085Knowledge Foundation, 20160139
Available from: 2017-03-22 Created: 2017-03-22 Last updated: 2019-10-14Bibliographically approved
Abbaspour Asadollah, S., Sundmark, D., Eldh, S., Hansson, H. & Afza, W. (2017). 10 Years of research on debugging concurrent and multicore software: a systematic mapping study. Software quality journal, 25(1), 49-82
Open this publication in new window or tab >>10 Years of research on debugging concurrent and multicore software: a systematic mapping study
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2017 (English)In: Software quality journal, ISSN 0963-9314, E-ISSN 1573-1367, Vol. 25, no 1, p. 49-82Article in journal (Refereed) Published
Abstract [en]

Debugging – the process of identifying, localizing and fixing bugs – is a key activity in software development. Due to issues such as non-determinism and difficulties of reproducing failures, debugging concurrent software is significantly more challenging than debugging sequential software. A number of methods, models and tools for debugging concurrent and multicore software have been proposed, but the body of work partially lacks a common terminology and a more recent view of the problems to solve. This suggests the need for a classification, and an up-to-date comprehensive overview of the area. 

This paper presents the results of a systematic mapping study in the field of debugging of concurrent and multicore software in the last decade (2005– 2014). The study is guided by two objectives: (1) to summarize the recent publication trends and (2) to clarify current research gaps in the field.

Through a multi-stage selection process, we identified 145 relevant papers. Based on these, we summarize the publication trend in the field by showing distribution of publications with respect to year , publication venues , representation of academia and industry , and active research institutes . We also identify research gaps in the field based on attributes such as types of concurrency bugs, types of debugging processes , types of research  and research contributions.

The main observations from the study are that during the years 2005–2014: (1) there is no focal conference or venue to publish papers in this area, hence a large variety of conferences and journal venues (90) are used to publish relevant papers in this area; (2) in terms of publication contribution, academia was more active in this area than industry; (3) most publications in the field address the data race bug; (4) bug identification is the most common stage of debugging addressed by articles in the period; (5) there are six types of research approaches found, with solution proposals being the most common one; and (6) the published papers essentially focus on four different types of contributions, with ”methods” being the type most common one.

We can further conclude that there is still quite a number of aspects that are not sufficiently covered in the field, most notably including (1) exploring correction  and fixing bugs  in terms of debugging process; (2) order violation, suspension  and starvation  in terms of concurrency bugs; (3) validation and evaluation research  in the matter of research type; (4) metric  in terms of research contribution. It is clear that the concurrent, parallel and multicore software community needs broader studies in debugging.This systematic mapping study can help direct such efforts.

National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-31419 (URN)10.1007/s11219-015-9301-7 (DOI)000394524400003 ()2-s2.0-84955305408 (Scopus ID)
Projects
SYNOPSIS project
Available from: 2016-04-12 Created: 2016-04-12 Last updated: 2018-10-29Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-5032-2310

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