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Ahmadilivani, M. H., Taheri, M., Raik, J., Daneshtalab, M. & Jenihhin, M. (2024). A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. ACM Computing Surveys, 56(6), Article ID 141.
Öppna denna publikation i ny flik eller fönster >>A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks
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2024 (Engelska)Ingår i: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341, Vol. 56, nr 6, artikel-id 141Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

Artificial Intelligence (AI) and, in particular, Machine Learning (ML), have emerged to be utilized in various applications due to their capability to learn how to solve complex problems. Over the past decade, rapid advances in ML have presented Deep Neural Networks (DNNs) consisting of a large number of neurons and layers. DNN Hardware Accelerators (DHAs) are leveraged to deploy DNNs in the target applications. Safety-critical applications, where hardware faults/errors would result in catastrophic consequences, also benefit from DHAs. Therefore, the reliability of DNNs is an essential subject of research. In recent years, several studies have been published accordingly to assess the reliability of DNNs. In this regard, various reliability assessment methods have been proposed on a variety of platforms and applications. Hence, there is a need to summarize the state-of-the-art to identify the gaps in the study of the reliability of DNNs. In this work, we conduct a Systematic Literature Review (SLR) on the reliability assessment methods of DNNs to collect relevant research works as much as possible, present a categorization of them, and address the open challenges. Through this SLR, three kinds of methods for reliability assessment of DNNs are identified, including Fault Injection (FI), Analytical, and Hybrid methods. Since the majority of works assess the DNN reliability by FI, we characterize different approaches and platforms of the FI method comprehensively. Moreover, Analytical and Hybrid methods are propounded. Thus, different reliability assessment methods for DNNs have been elaborated on their conducted DNN platforms and reliability evaluation metrics. Finally, we highlight the advantages and disadvantages of the identified methods and address the open challenges in the research area. We have concluded that Analytical and Hybrid methods are light-weight yet sufficiently accurate and have the potential to be extended in future research and to be utilized in establishing novel DNN reliability assessment frameworks.

Ort, förlag, år, upplaga, sidor
ASSOC COMPUTING MACHINERY, 2024
Nyckelord
Reliability assessment, deep neural networks, DNN hardware accelerator, fault injection
Nationell ämneskategori
Elektroteknik och elektronik
Identifikatorer
urn:nbn:se:mdh:diva-66411 (URN)10.1145/3638242 (DOI)001208566200007 ()2-s2.0-85188964919 (Scopus ID)
Tillgänglig från: 2024-04-10 Skapad: 2024-04-10 Senast uppdaterad: 2024-05-15Bibliografiskt granskad
Taheri, M., Daneshtalab, M., Raik, J., Jenihhin, M., Pappalardo, S., Jimenez, P., . . . Bosio, A. (2024). SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. In: 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS): . Paper presented at Proceedings - 2024 27th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2024 (pp. 19-24). Institute of Electrical and Electronics Engineers Inc.
Öppna denna publikation i ny flik eller fönster >>SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
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2024 (Engelska)Ingår i: 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS), Institute of Electrical and Electronics Engineers Inc. , 2024, s. 19-24Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

Systolic array has emerged as a prominent archi-tecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency performance essen-tial for deploying DNNs across diverse applications. However, when used in safety-critical applications, reliability assessment is mandatory to guarantee the correct behavior of DNN accelerators. While fault injection stands out as a well-established practical and robust method for reliability assessment, it is still a very time-consuming process. This paper addresses the time efficiency issue by introducing a novel hierarchical software-based hardware-aware fault injection strategy tailored for systolic array-based DNN accelerators. The uniform Recurrent Equations system is used for software modeling of the systolic-array core of the DNN accelerators. The approach demonstrates a reduction of the fault injection time up to 3 × compared to the state-of-the-art hybrid (software/hardware) hardware-aware fault injection frameworks and more than 2000 × compared to RT-level fault injection frameworks - without compromising accuracy. Additionally, we propose and evaluate a new reliability metric through experimental assessment. The performance of the framework is studied on state-of-the-art DNN benchmarks.

Ort, förlag, år, upplaga, sidor
Institute of Electrical and Electronics Engineers Inc., 2024
Nyckelord
deep neural networks, fault simulation, hardware accelerator, reliability, resilience assessment, systolic array, Benchmarking, Reliability analysis, Safety engineering, Software testing, Systolic arrays, Fault injection, Fault's simulations, Hardware accelerators, High-low, High-throughput, Low latency, Neural network hardware, Reliability assessments, State of the art
Nationell ämneskategori
Data- och informationsvetenskap
Identifikatorer
urn:nbn:se:mdh:diva-66660 (URN)10.1109/DDECS60919.2024.10508925 (DOI)2-s2.0-85192792789 (Scopus ID)9798350359343 (ISBN)
Konferens
Proceedings - 2024 27th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2024
Tillgänglig från: 2024-05-22 Skapad: 2024-05-22 Senast uppdaterad: 2024-05-22Bibliografiskt granskad
Satka, Z., Ashjaei, S. M., Fotouhi, H., Daneshtalab, M., Sjödin, M. & Mubeen, S. (2023). A comprehensive systematic review of integration of time sensitive networking and 5G communication. Journal of systems architecture, 138, Article ID 102852.
Öppna denna publikation i ny flik eller fönster >>A comprehensive systematic review of integration of time sensitive networking and 5G communication
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2023 (Engelska)Ingår i: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 138, artikel-id 102852Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

Many industrial real-time applications in various domains, e.g., automotive, industrial automation, industrial IoT, and industry 4.0, require ultra-low end-to-end network latency, often in the order of 10 milliseconds or less. The IEEE 802.1 time-sensitive networking (TSN) is a set of standards that supports the required low-latency wired communication with ultra-low jitter. The flexibility of such a wired connection can be increased if it is integrated with a mobile wireless network. The fifth generation of cellular networks (5G) is capable of supporting the required levels of network latency with the Ultra-Reliable Low Latency Communication (URLLC) service. To fully utilize the potential of these two technologies (TSN and 5G) in industrial applications, seamless integration of the TSN wired-based network with the 5G wireless-based network is needed. In this article, we provide a comprehensive and well-structured snapshot of the existing research on TSN-5G integration. In this regard, we present the planning, execution, and analysis results of the systematic review. We also identify the trends, technical characteristics, and potential gaps in the state of the art, thus highlighting future research directions in the integration of TSN and 5G communication technologies. We notice that 73% of the primary studies address the time synchronization in the integration of TSN and 5G technologies, introducing approaches with an accuracy starting from the levels of hundred nanoseconds to one microsecond. Majority of primary studies aim at optimizing communication latency in their approach, which is a key quality attribute in automotive and industrial automation applications today.

Ort, förlag, år, upplaga, sidor
Elsevier, 2023
Nyckelord
Time-Sensitive Networking, TSN, 5G, TSN-5G, URLLC, Industry 4.0
Nationell ämneskategori
Kommunikationssystem Inbäddad systemteknik
Forskningsämne
datavetenskap
Identifikatorer
urn:nbn:se:mdh:diva-62062 (URN)10.1016/j.sysarc.2023.102852 (DOI)000956098500001 ()2-s2.0-85149863981 (Scopus ID)
Projekt
PROVIDENT
Forskningsfinansiär
Vinnova, 16533
Tillgänglig från: 2023-03-13 Skapad: 2023-03-13 Senast uppdaterad: 2023-05-17Bibliografiskt granskad
Asadi, M., Poursalim, F., Loni, M., Daneshtalab, M., Sjödin, M. & Gharehbaghi, A. (2023). Accurate detection of paroxysmal atrial fibrillation with certified-GAN and neural architecture search. Scientific Reports, 13(1)
Öppna denna publikation i ny flik eller fönster >>Accurate detection of paroxysmal atrial fibrillation with certified-GAN and neural architecture search
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2023 (Engelska)Ingår i: Scientific Reports, E-ISSN 2045-2322, Vol. 13, nr 1Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

This paper presents a novel machine learning framework for detecting PxAF, a pathological characteristic of electrocardiogram (ECG) that can lead to fatal conditions such as heart attack. To enhance the learning process, the framework involves a generative adversarial network (GAN) along with a neural architecture search (NAS) in the data preparation and classifier optimization phases. The GAN is innovatively invoked to overcome the class imbalance of the training data by producing the synthetic ECG for PxAF class in a certified manner. The effect of the certified GAN is statistically validated. Instead of using a general-purpose classifier, the NAS automatically designs a highly accurate convolutional neural network architecture customized for the PxAF classification task. Experimental results show that the accuracy of the proposed framework exhibits a high value of 99.0% which not only enhances state-of-the-art by up to 5.1%, but also improves the classification performance of the two widely-accepted baseline methods, ResNet-18, and Auto-Sklearn, by [Formula: see text] and [Formula: see text].

Ort, förlag, år, upplaga, sidor
NLM (Medline), 2023
Nyckelord
Atrial Fibrillation, Electrocardiography, Humans, Machine Learning, Neural Networks, Computer, artificial neural network, human
Nationell ämneskategori
Datorsystem
Identifikatorer
urn:nbn:se:mdh:diva-63915 (URN)10.1038/s41598-023-38541-8 (DOI)001030642400009 ()37452165 (PubMedID)2-s2.0-85164756079 (Scopus ID)
Tillgänglig från: 2023-07-26 Skapad: 2023-07-26 Senast uppdaterad: 2023-09-13Bibliografiskt granskad
Mousavi, H., Zoljodi, A. & Daneshtalab, M. (2023). Analysing Robustness of Tiny Deep Neural Networks. In: Commun. Comput. Info. Sci.: . Paper presented at Communications in Computer and Information Science (pp. 150-159). Springer Science and Business Media Deutschland GmbH
Öppna denna publikation i ny flik eller fönster >>Analysing Robustness of Tiny Deep Neural Networks
2023 (Engelska)Ingår i: Commun. Comput. Info. Sci., Springer Science and Business Media Deutschland GmbH , 2023, s. 150-159Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

Real-world applications that are safety-critical and resource-constrained necessitate using compact and robust Deep Neural Networks (DNNs) against adversarial data perturbation. MobileNet-tiny has been introduced as a compact DNN to deploy on edge devices to reduce the size of networks. To make DNNs more robust against adversarial data, adversarial training methods have been proposed. However, recent research has investigated the robustness of large-scale DNNs (such as WideResNet), but the robustness of tiny DNNs has not been analysed. In this paper, we analyse how the width of the blocks in MobileNet-tiny affects the robustness of the network against adversarial data perturbation. Specifically, we evaluate natural accuracy, robust accuracy, and perturbation instability metrics on the MobileNet-tiny with various inverted bottleneck blocks with different configurations. We generate configurations for inverted bottleneck blocks using different width-multipliers and expand-ratio hyper-parameters. We discover that expanding the width of the blocks in MobileNet-tiny can improve the natural and robust accuracy but increases perturbation instability. In addition, after a certain threshold, increasing the width of the network does not have significant gains in robust accuracy and increases perturbation instability. We also analyse the relationship between the width-multipliers and expand-ratio hyper-parameters with the Lipchitz constant, both theoretically and empirically. It shows that wider inverted bottleneck blocks tend to have significant perturbation instability. These architectural insights can be useful in developing adversarially robust tiny DNNs for edge devices.

Ort, förlag, år, upplaga, sidor
Springer Science and Business Media Deutschland GmbH, 2023
Nyckelord
Adversarial data perturbation, Adversarial training, Lipchitz constant, Robustness analysis, Safety engineering, Stability, Data perturbation, Hyper-parameter, Large-scales, Real-world, Recent researches, Training methods, Deep neural networks
Nationell ämneskategori
Data- och informationsvetenskap
Identifikatorer
urn:nbn:se:mdh:diva-64432 (URN)10.1007/978-3-031-42941-5_14 (DOI)2-s2.0-85171970100 (Scopus ID)9783031429408 (ISBN)
Konferens
Communications in Computer and Information Science
Tillgänglig från: 2023-10-09 Skapad: 2023-10-09 Senast uppdaterad: 2023-10-09Bibliografiskt granskad
Ahmadilivani, M. H., Raik, J., Daneshtalab, M. & Kuusik, A. (2023). Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks. In: Proc. IEEE Int. Symp. Defect Fault Toler. VLSI Nanotechnol. Syst., DFT: . Paper presented at Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT. Institute of Electrical and Electronics Engineers Inc.
Öppna denna publikation i ny flik eller fönster >>Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks
2023 (Engelska)Ingår i: Proc. IEEE Int. Symp. Defect Fault Toler. VLSI Nanotechnol. Syst., DFT, Institute of Electrical and Electronics Engineers Inc. , 2023Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

The reliability of Artificial Neural Networks (ANNs) has emerged as a prominent research topic due to their increasing utilization in safety-critical applications. Long Short-Term Memory (LSTM) ANNs have demonstrated significant advantages in healthcare applications, primarily attributed to their robust processing of time-series data and memory-facilitated capabilities. This paper, for the first time, presents a comprehensive and fine-grain analysis of the resilience of LSTM-based ANNs in the context of gait analysis using fault injection into weights. Additionally, we improve their resilience by replacing faulty weights with zero, enabling ANNs to withstand environments that are up to 20 times harsher while experiencing up to 7 times fewer critical faults than an unprotected ANN.

Ort, förlag, år, upplaga, sidor
Institute of Electrical and Electronics Engineers Inc., 2023
Nyckelord
Brain, Safety engineering, Fault injection, Fine-grain analysis, Health care application, Neural-networks, Research topics, Robust processing, Safety critical applications, Time-series data, Long short-term memory
Nationell ämneskategori
Elektroteknik och elektronik
Identifikatorer
urn:nbn:se:mdh:diva-65145 (URN)10.1109/DFT59622.2023.10313559 (DOI)2-s2.0-85179010250 (Scopus ID)9798350315004 (ISBN)
Konferens
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
Tillgänglig från: 2023-12-21 Skapad: 2023-12-21 Senast uppdaterad: 2023-12-21Bibliografiskt granskad
Taheri, M., Ahmadilivani, M. H., Jenihhin, M., Daneshtalab, M. & Raik, J. (2023). APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. In: Proceedings - 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023: . Paper presented at 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, 3-5 May 2023, Tallin, Estonia (pp. 124-127). Institute of Electrical and Electronics Engineers Inc.
Öppna denna publikation i ny flik eller fönster >>APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors
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2023 (Engelska)Ingår i: Proceedings - 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Institute of Electrical and Electronics Engineers Inc. , 2023, s. 124-127Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

Nowadays, the extensive exploitation of Deep Neural Networks (DNNs) in safety-critical applications raises new reliability concerns. In practice, methods for fault injection by emulation in hardware are efficient and widely used to study the resilience of DNN architectures for mitigating reliability issues already at the early design stages. However, the state-of-the-art methods for fault injection by emulation incur a spectrum of time-, design-and control-complexity problems. To overcome these issues, a novel resiliency assessment method called APPRAISER is proposed that applies functional approximation for a non-conventional purpose and employs approximate computing errors for its interest. By adopting this concept in the resiliency assessment domain, APPRAISER provides thousands of times speed-up in the assessment process, while keeping high accuracy of the analysis. In this paper, APPRAISER is validated by comparing it with state-of-the-art approaches for fault injection by emulation in FPGA. By this, the feasibility of the idea is demonstrated, and a new perspective in resiliency evaluation for DNNs is opened.

Ort, förlag, år, upplaga, sidor
Institute of Electrical and Electronics Engineers Inc., 2023
Nyckelord
approximate computing, Deep Neural Networks, fault injection, reliability, resiliency assessment, Reliability analysis, Safety engineering, Software testing, Approximation errors, Early design stages, Fault resilience, Network faults, Neural network architecture, Safety critical applications, State-of-the-art methods
Nationell ämneskategori
Datorsystem
Identifikatorer
urn:nbn:se:mdh:diva-63672 (URN)10.1109/DDECS57882.2023.10139468 (DOI)001012062000024 ()2-s2.0-85161915380 (Scopus ID)9798350332773 (ISBN)
Konferens
26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, 3-5 May 2023, Tallin, Estonia
Tillgänglig från: 2023-06-28 Skapad: 2023-06-28 Senast uppdaterad: 2023-12-04Bibliografiskt granskad
Berisa, A., Panjevic, A., Kovac, I., Lyngbäck, H., Ashjaei, S. M., Daneshtalab, M., . . . Mubeen, S. (2023). Comparative Evaluation of Various Generations of Controller Area Network Based on Timing Analysis. In: IEEE Int. Conf. Emerging Technol. Factory Autom., ETFA: . Paper presented at IEEE International Conference on Emerging Technologies and Factory Automation, ETFA. Institute of Electrical and Electronics Engineers Inc.
Öppna denna publikation i ny flik eller fönster >>Comparative Evaluation of Various Generations of Controller Area Network Based on Timing Analysis
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2023 (Engelska)Ingår i: IEEE Int. Conf. Emerging Technol. Factory Autom., ETFA, Institute of Electrical and Electronics Engineers Inc. , 2023Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

This paper performs a comparative evaluation of various generations of Controller Area Network (CAN), including the classical CAN, CAN Flexible Data-Rate (FD), and CAN Extra Long (XL). We utilize response-time analysis for the evaluation. In this regard, we identify that the state of the art lacks the response-time analysis for CAN XL. Hence, we discuss the worst-case transmission times calculations for CAN XL frames and incorporate them to the existing analysis for CAN to support response-time analysis of CAN XL frames. Using the extended analysis, we perform a comparative evaluation of the three generations of CAN by analyzing an automotive industrial use case. In crux, we show that using CAN FD is more advantageous than the classical CAN and CAN XL when using frames with payloads of up to 8 bytes, despite the fact that CAN XL supports higher bit rates. For frames with 12-64 bytes payloads, CAN FD performs better than CAN XL when running at the same bit rate, but CAN XL performs better when running at a higher bit rate. Additionally, we discovered that CAN XL performs better than the classical CAN and CAN FD when the frame payload is over 64 bytes, even if it runs at the same or higher bit rates than CAN FD.

Ort, förlag, år, upplaga, sidor
Institute of Electrical and Electronics Engineers Inc., 2023
Nyckelord
automotive, CAN FD, CAN XL, Controller Area Network, Control system synthesis, Controllers, Finite difference method, Process control, Automotives, Classical controllers, Comparative evaluations, Controller area network flexible data-rate, Controller area network XL, Controller-area network, Data-rate, Response-time analysis, Timing circuits
Nationell ämneskategori
Data- och informationsvetenskap
Identifikatorer
urn:nbn:se:mdh:diva-64693 (URN)10.1109/ETFA54631.2023.10275549 (DOI)2-s2.0-85175488822 (Scopus ID)9798350339918 (ISBN)
Konferens
IEEE International Conference on Emerging Technologies and Factory Automation, ETFA
Tillgänglig från: 2023-11-09 Skapad: 2023-11-09 Senast uppdaterad: 2024-01-18Bibliografiskt granskad
Mousavi, H., Loni, M., Alibeigi, M. & Daneshtalab, M. (2023). DASS: Differentiable Architecture Search for Sparse Neural Networks. ACM Transactions on Embedded Computing Systems, 22(5 s), Article ID 105.
Öppna denna publikation i ny flik eller fönster >>DASS: Differentiable Architecture Search for Sparse Neural Networks
2023 (Engelska)Ingår i: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 22, nr 5 s, artikel-id 105Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

The deployment of Deep Neural Networks (DNNs) on edge devices is hindered by the substantial gap between performance requirements and available computational power. While recent research has made significant strides in developing pruning methods to build a sparse network for reducing the computing overhead of DNNs, there remains considerable accuracy loss, especially at high pruning ratios. We find that the architectures designed for dense networks by differentiable architecture search methods are ineffective when pruning mechanisms are applied to them. The main reason is that the current methods do not support sparse architectures in their search space and use a search objective that is made for dense networks and does not focus on sparsity.This paper proposes a new method to search for sparsity-friendly neural architectures. It is done by adding two new sparse operations to the search space and modifying the search objective. We propose two novel parametric SparseConv and SparseLinear operations in order to expand the search space to include sparse operations. In particular, these operations make a flexible search space due to using sparse parametric versions of linear and convolution operations. The proposed search objective lets us train the architecture based on the sparsity of the search space operations. Quantitative analyses demonstrate that architectures found through DASS outperform those used in the state-of-the-art sparse networks on the CIFAR-10 and ImageNet datasets. In terms of performance and hardware effectiveness, DASS increases the accuracy of the sparse version of MobileNet-v2 from 73.44% to 81.35% (+7.91% improvement) with a 3.87× faster inference time.

Ort, förlag, år, upplaga, sidor
Association for Computing Machinery, 2023
Nyckelord
image classification, network sparsification, Neural architecture search, optimization, Deep neural networks, Network architecture, Dense network, Images classification, Neural architectures, Optimisations, Search spaces, Sparse network, Sparse neural networks, Sparsification
Nationell ämneskategori
Elektroteknik och elektronik
Identifikatorer
urn:nbn:se:mdh:diva-64424 (URN)10.1145/3609385 (DOI)001074334300008 ()2-s2.0-85171744110 (Scopus ID)
Tillgänglig från: 2023-10-09 Skapad: 2023-10-09 Senast uppdaterad: 2023-10-25Bibliografiskt granskad
Taheri, M., Riazati, M., Ahmadilivani, M. H., Jenihhin, M., Daneshtalab, M., Raik, J., . . . Lisper, B. (2023). DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. In: Proceedings - International Symposium on Quality Electronic Design, ISQED: . Paper presented at 24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, 5 April 2023 through 7 April 2023. IEEE Computer Society
Öppna denna publikation i ny flik eller fönster >>DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators
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2023 (Engelska)Ingår i: Proceedings - International Symposium on Quality Electronic Design, ISQED, IEEE Computer Society , 2023Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

While the role of Deep Neural Networks (DNNs) in a wide range of safety-critical applications is expanding, emerging DNNs experience massive growth in terms of computation power. It raises the necessity of improving the reliability of DNN accelerators yet reducing the computational burden on the hardware platforms, i.e. reducing the energy consumption and execution time as well as increasing the efficiency of DNN accelerators. Therefore, the trade-off between hardware performance, i.e. area, power and delay, and the reliability of the DNN accelerator implementation becomes critical and requires tools for analysis.In this paper, we propose a framework DeepAxe for design space exploration for FPGA-based implementation of DNNs by considering the trilateral impact of applying functional approximation on accuracy, reliability and hardware performance. The framework enables selective approximation of reliability-critical DNNs, providing a set of Pareto-optimal DNN implementation design space points for the target resource utilization requirements. The design flow starts with a pre-trained network in Keras, uses an innovative high-level synthesis environment DeepHLS and results in a set of Pareto-optimal design space points as a guide for the designer. The framework is demonstrated on a case study of custom and state-of-the-art DNNs and datasets. 

Ort, förlag, år, upplaga, sidor
IEEE Computer Society, 2023
Nyckelord
approximate computing, deep neural networks, fault simulation, reliability, resiliency assessment
Nationell ämneskategori
Datorsystem
Identifikatorer
urn:nbn:se:mdh:diva-63499 (URN)10.1109/ISQED57927.2023.10129353 (DOI)001013619400058 ()2-s2.0-85161606608 (Scopus ID)9798350334753 (ISBN)
Konferens
24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, 5 April 2023 through 7 April 2023
Tillgänglig från: 2023-06-21 Skapad: 2023-06-21 Senast uppdaterad: 2023-10-09Bibliografiskt granskad
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